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参数资料
| 型号： | KIT908EINTFC |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 31/49页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL 908E625 QUAD W/MCU/LIN |
| 标准包装： | 1 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
37
908E625
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
is activated. Once this function is enabled, it is not possible to
disable it via software.
If the timer reaches end value and AWDRE is set, a
system reset is initiated. Operations of the watchdog function
cease in STOP mode. Normal operation will be continued
when the system is back to RUN mode.
To prevent a watchdog reset, the watchdog timeout
counter must be reset before it reaches the end value. This is
done by a write to the AWDRST bit in the AWDCTL Register.
PERIODIC INTERRUPT
Periodic interrupt is only available in STOP mode. It is
enabled by setting the AWDIE bit in the AWDCTL Register. If
AWDIE is set, the AWD wakes up the system after a fixed
period of time. This time period can be selected with bit
AWDR in the AWDCTL Register.
CYCLIC WAKE-UP
The cyclic wake-up feature is only available in STOP
mode. If this feature is enabled, the selected Hall-effect
sensor input pins are switched on and sensed. If a “1” is
detected on one of these inputs and the interrupt for the Hall-
effect sensors is enabled, a system wake-up is performed.
(Switch on main voltage regulator and assert IRQ_A to the
microcontroller).
AUTONOMOUS WATCHDOG CONTROL
REGISTER (AWDCTL)
Autonomous Watchdog Reset Bit (AWDRST)
This write-only bit resets the Autonomous Watchdog
timeout period. AWDRST always reads 0. Reset clears
AWDRST bit.
1 = Reset AWD and restart timeout period
0 = No effect
Autonomous Watchdog Reset Enable Bit (AWDRE)
This read/write bit enables resets on AWD timeouts. A
reset on the RST_A is only asserted when the device is in
RUN mode. AWDRE is one time setable (write once) after
each reset. Reset clears the AWDRE bit.
1 = Autonomous watchdog enabled
0 = Autonomous watchdog disabled
Autonomous Watchdog Interrupt Enable Bit (AWDIE)
This read/write bit enables CPU interrupts by the
Autonomous Watchdog timeout flag, AWFD. IRQ_A is only
asserted when the device is in STOP mode. Reset clears the
AWDIE bit.
1 = CPU interrupt requests from AWDF enabled
0 = CPU interrupt requests from AWDF disabled
Autonomous Watchdog Cyclic Check (AWDCC)
This read/write bit enables the cyclic check of the two pin
Hall-effect sensor and the analog inputs. Reset clears the
AWDCC bit.
1 = Cyclic check of the Hall-effect sensor and analog
port
0 = No cyclic check of the Hall-effect sensor and analog
port
Autonomous Watchdog Timeout Flag Bit (AWDF)
This read/write flag is set when the Autonomous
Watchdog has timed out. Clear AWDF by writing a Logic [1]
to AWDF. Clearing AWDF also resets the AWD counter and
starts a new timeout period. Reset clears the AWDF bit.
Writing a Logic [0] to AWDF has no effect.
1 = AWD has timed out
0 = AWD has not yet timed out
Autonomous Watchdog Rate Bit (AWDR)
This read/write bit selects the clock rate of the
Autonomous Watchdog. Reset clears the AWDR bit.
1 = Fast rate selected (10 ms)
0 = Slow rate selected (20 ms)
VOLTAGE REGULATOR
The 908E625 chip contains a low power, low drop voltage
regulator to provide internal power and external power for the
MCU. The on-chip regulator consist of two elements, the
main voltage regulator and the low voltage reset circuit.
The VDD regulator accepts a unregulated input supply and
provides a regulated VDD supply to all digital sections of the
device. The output of the regulator is also connected to the
VDD pin to provide the 5.0 V to the microcontroller.
RUN Mode
During RUN mode the main voltage regulator is on. It
provides a regulated supply to all digital sections.
Register Name and Address: AWDCTL - $0a
Bits
7
6
5
4
3
2
1
0
Read
00
0
AWDR
E
AWDI
E
AWDC
C
AWDF
AWD
R
Write
AWDRS
T
Reset
00
0
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