参数资料
型号: KSZ8031RNL TR
厂商: Micrel Inc
文件页数: 21/43页
文件大小: 0K
描述: TXRX PHY 100BASE TX 3.3V 24QFN
标准包装: 1
类型: PHY 收发器
驱动器/接收器数: 1/1
规程: RMII
电源电压: 1.8V,2.5V,3.3V
安装类型: 表面贴装
封装/外壳: 24-VFQFN 裸露焊盘
供应商设备封装: 24-QFN(4x4)
包装: 标准包装
配用: 576-3862-ND - BOARD EVALUATION FOR KSZ8031RNL
其它名称: 576-3843-6
Micrel, Inc.
KSZ8021RNL / KSZ8031RNL
August 2010
28
M9999-082710-1.0
Register Description (Continued)
Address
Name
Description
Mode
(1)
Default
Register 7h – Auto-Negotiation Next Page
7.15
Next Page
1 = Additional next page(s) will follow
0 = Last page
RW
0
7.14
Reserved
RO
0
7.13
Message Page
1 = Message page
0 = Unformatted page
RW
1
7.12
Acknowledge2
1 = Will comply with message
0 = Cannot comply with message
RW
0
7.11
Toggle
1 = Previous value of the transmitted link code
word equaled logic one
0 = Logic zero
RO
0
7.10:0
Message Field
11-bit wide field to encode 2048 messages
RW
000_0000_0001
Register 8h – Link Partner Next Page Ability
8.15
Next Page
1 = Additional Next Page(s) will follow
0 = Last page
RO
0
8.14
Acknowledge
1 = Successful receipt of link word
0 = No successful receipt of link word
RO
0
8.13
Message Page
1 = Message page
0 = Unformatted page
RO
0
8.12
Acknowledge2
1 = Able to act on the information
0 = Not able to act on the information
RO
0
8.11
Toggle
1 = Previous value of transmitted link code
word equal to logic zero
0 = Previous value of transmitted link code
word equal to logic one
RO
0
8.10:0
Message Field
RO
000_0000_0000
Register 10h – Digital Reserved Control
10.15:5
Reserved
RW
0000_0000_000
10.4
PLL off
1 = Turn PLL off automatically in EDPD mode.
0 = Keep PLL on in EDPD mode.
See also register 18h, bit [11] for EDPD mode.
RW
0
10.3:0
Reserved
RW
0000
Register 11h – AFE Control 1
11.15:6
Reserved
RW
0000_0000_00
11.5
Slow Oscillator
Mode Enable
Slow Oscillator Mode is used to disconnect the
input reference crystal/clock on the XI pin and
select the on-chip slow oscillator when the
KSZ8021/31RNL device is not in use after
power-up.
1 = Enable
0 = Disable
This bit automatically sets software power down
to the analog side when enabled.
RW
0
11.4:0
Reserved
RW
0_0000
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