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| 型号： | KSZ8031RNL TR |
| 厂商： | Micrel Inc |
| 文件页数： | 7/43页 |
| 文件大小： | 0K |
| 描述： | TXRX PHY 100BASE TX 3.3V 24QFN |
| 标准包装： | 1 |
| 类型： | PHY 收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | RMII |
| 电源电压： | 1.8V，2.5V，3.3V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN（4x4） |
| 包装： | 标准包装 |
| 配用： | 576-3862-ND - BOARD EVALUATION FOR KSZ8031RNL |
| 其它名称： | 576-3843-6 |
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Micrel, Inc.
KSZ8021RNL / KSZ8031RNL
August 2010
15
M9999-082710-1.0
RMII Data Interface
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides
a common interface between physical layer and MAC layer devices, and has the following key characteristics:
Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, 1 pin for the 50MHz reference clock).
10Mbps and 100Mbps data rates are supported at both half and full duplex.
Data transmission and reception are independent and belong to separate signal groups.
Transmit data and receive data are each 2-bit wide, a dibit.
RMII Signal Definition
The following table describes the RMII signals. Refer to RMII Specification v1.2 for detailed information.
RMII
Signal Name
Direction
(with respect to PHY,
KSZ8021/31RNL signal)
Direction
(with respect to
MAC)
Description
REF_CLK
Output (25MHz Clock Mode) /
<no connect> (50MHz Clock
Mode)
Input /
Input or <no connect>
Synchronous 50MHz reference clock for
receive, transmit and control interface
TXEN
Input
Output
Transmit Enable
TXD[1:0]
Input
Output
Transmit Data [1:0]
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data [1:0]
RXER
Output
Input, or (not
required)
Receive Error
Table 1. RMII Signal Description
Reference Clock (REF_CLK)
REF_CLK is a continuous 50MHz clock that provides the timing reference for TXEN, TXD[1:0], CRS_DV, RXD[1:0], and
RXER.
For RMII – 25MHz Clock Mode, the KSZ8021/31RNL generates and outputs the 50MHz RMII REF_CLK to the MAC at
REF_CLK (Pin 16).
For RMII – 50MHz Clock Mode, the KSZ8021/31RNL takes in the 50MHz RMII REF_CLK from the MAC or system board
at XI (Pin 8) and has the REF_CLK (pin 16) left as a no connect.
Transmit Enable (TXEN)
TXEN indicates that the MAC is presenting dibits on TXD[1:0] for transmission. It is asserted synchronously with the first
dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the RMII, and is negated
prior to the first REF_CLK following the final dibit of a frame.
TXEN transitions synchronously with respect to REF_CLK.
Transmit Data [1:0] (TXD[1:0])
TXD[1:0] transitions synchronously with respect to REF_CLK. When TXEN is asserted, TXD[1:0] are accepted for
transmission by the PHY.
TXD[1:0] is ”00” to indicate idle when TXEN is de-asserted. Values other than “00” on TXD[1:0] while TXEN is de-asserted
are ignored by the PHY.
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted by the PHY when the receive medium is non-idle. It is asserted asynchronously on detection of
carrier. This is when squelch is passed in 10Mbps mode, and when two non-contiguous zeroes in 10 bits are detected in
100Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.
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| KSZ8041FTLI | 功能描述:以太网 IC Physical Layer Transceiver 10/100BASE-FX (Lead Free) RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray |
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