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| 型号： | KSZ8041NL-EVAL |
| 厂商： | Micrel Inc |
| 文件页数： | 13/54页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR KSZ8041NL |
| 标准包装： | 1 |
| 主要目的： | 接口，以太网 PHY |
| 嵌入式： | 否 |
| 已用 IC / 零件： | KSZ8041NL |
| 主要属性： | 单芯片 PHY，10BASE-T/100BASE-TX |
| 次要属性： | MII，RMII，HP 自动 MDI，MDI-X 自动极性校正 |
| 已供物品： | 板 |
| 产品目录页面： | 1114 (CN2011-ZH PDF) |
| 相关产品： | 576-3296-5-ND - IC TXRX PHY 10/100 AUTO 32-MLF 576-2109-6-ND - IC TXRX PHY 10/100 LV/LP 32-MLF 576-2109-1-ND - IC TXRX PHY 10/100 LV/LP 32-MLF 576-2109-2-ND - IC TXRX PHY 10/100 LV/LP 32-MLF KSZ8041NLA3TR-ND - TRANSCEIVER 10/100 32-MLF 576-1645-6-ND - IC TXRX PHY 10/100 LV/LP 32-MLF 576-1645-1-ND - IC TXRX PHY 10/100 LV/LP 32-MLF 576-1645-2-ND - IC TXRX PHY 10/100 LV/LP 32-MLF |
| 其它名称： | 576-1621 |
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Micrel, Inc.
KSZ8041NL/RNL
September 2010
20
M9999-090910-1.4
Functional Description
The KSZ8041NL is a single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3u Specification.
On the media side, the KSZ8041NL supports 10Base-T and 100Base-TX with HP auto MDI/MDI-X for reliable detection of
and correction for straight-through and crossover cables.
The KSZ8041NL offers a choice of MII or RMII data interface connection with the MAC processor. The MII management
bus option gives the MAC processor complete access to the KSZ8041NL control and status registers. Additionally, an
interrupt pin eliminates the need for the processor to poll for PHY status change.
Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the
design more efficient and allow for lower power consumption and smaller chip die size.
The KSZ8041RNL is an enhanced RMII version of the KSZ8041NL that does not require a 50MHz system clock. It uses a
25MHz crystal for its input reference clock and outputs a 50MHz RMII reference clock to the MAC.
100Base-TX Transmit
The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit
stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data is
further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output.
The output current is set by an external 6.49k
Ω 1% resistor for the 1:1 transformer ratio. It has typical rise/fall times of 4
ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot and timing jitter. The wave-
shaped 10Base-T output drivers are also incorporated into the 100Base-TX drivers.
100Base-TX Receive
The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair
cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
PLL Clock Synthesizer
The KSZ8041NL/RNL generates 125M
Ηz, 25MΗz and 20MΗz clocks for system timing. Internal clocks are generated
from an external 25MHz crystal or oscillator. For the KSZ8041NL in RMII mode, these internal clocks are generated from
an external 50MHz oscillator or system clock.
Scrambler/De-scrambler (100Base-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander.
10Base-T Transmit
The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow for transmission using the same magnetic.
The drivers also perform internal wave-shaping and pre-emphasize, and output 10Base-T signals with a typical amplitude
of 2.5V peak. The 10Base-T signals have harmonic contents that are at least 27dB below the fundamental frequency
when driven by an all-ones Manchester-encoded signal.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| KSZ8041NLI | 制造商:Micrel Inc 功能描述:IC TXRX PHY 10/100 LV/LP 32-MLF*NIC* |
| KSZ8041NLI TR | 功能描述:以太网 IC Physical Layer Transceiver 10/100BASE-T/TX (Lead Free) RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray |
| KSZ8041NLITR | 制造商:Micrel 功能描述:Physical Layer Transceiver 1Ch 100Mbps |
| KSZ8041NLI-TR | 功能描述:1/1 Transceiver Full MII, RMII 32-MLF? (5x5) 制造商:microchip technology 系列:- 包装:剪切带（CT） 零件状态:有效 类型:收发器 协议:MII，RMII 驱动器/接收器数:1/1 双工:全 接收器滞后:- 数据速率:- 电压 - 电源:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘，32-MLF? 供应商器件封装:32-MLF?（5x5） 标准包装:1 |
| KSZ8041NLJ | 制造商:MICREL 制造商全称:Micrel Semiconductor 功能描述:10/100 Ethernet Transceiver with Extended Temperature Support |
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