参数资料
型号: KSZ8041NL-EVAL
厂商: Micrel Inc
文件页数: 17/54页
文件大小: 0K
描述: BOARD EVALUATION FOR KSZ8041NL
标准包装: 1
主要目的: 接口,以太网 PHY
嵌入式:
已用 IC / 零件: KSZ8041NL
主要属性: 单芯片 PHY,10BASE-T/100BASE-TX
次要属性: MII,RMII,HP 自动 MDI,MDI-X 自动极性校正
已供物品:
产品目录页面: 1114 (CN2011-ZH PDF)
相关产品: 576-3296-5-ND - IC TXRX PHY 10/100 AUTO 32-MLF
576-2109-6-ND - IC TXRX PHY 10/100 LV/LP 32-MLF
576-2109-1-ND - IC TXRX PHY 10/100 LV/LP 32-MLF
576-2109-2-ND - IC TXRX PHY 10/100 LV/LP 32-MLF
KSZ8041NLA3TR-ND - TRANSCEIVER 10/100 32-MLF
576-1645-6-ND - IC TXRX PHY 10/100 LV/LP 32-MLF
576-1645-1-ND - IC TXRX PHY 10/100 LV/LP 32-MLF
576-1645-2-ND - IC TXRX PHY 10/100 LV/LP 32-MLF
其它名称: 576-1621
Micrel, Inc.
KSZ8041NL/RNL
September 2010
24
M9999-090910-1.4
MII Signal Definition (KSZ8041NL only)
The Table 2 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
MII
Signal Name
Direction
(with respect to PHY,
KSZ8041NL signal)
Direction
(with respect to MAC)
Description
TXC
Output
Input
Transmit Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
TXEN
Input
Output
Transmit Enable
TXD[3:0]
Input
Output
Transmit Data [3:0]
RXC
Output
Input
Receive Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
RXDV
Output
Input
Receive Data Valid
RXD[3:0]
Output
Input
Receive Data [3:0]
RXER
Output
Input, or (not required)
Receive Error
CRS
Output
Input
Carrier Sense
COL
Output
Input
Collision Detection
Table 2. MII Signal Definition
Transmit Clock (TXC)
TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN and TXD[3:0].
TXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Transmit Enable (TXEN)
TXEN indicates the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII, and is negated
prior to the first TXC following the final nibble of a frame.
TXEN transitions synchronously with respect to TXC.
Transmit Data [3:0] (TXD[3:0])
TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted for transmission
by the PHY. TXD[3:0] is ”00” to indicate idle when TXEN is de-asserted. Values other than “00” on TXD[3:0] while TXEN
is de-asserted are ignored by the PHY.
Receive Clock (RXC)
RXC provides the timing reference for RXDV, RXD[3:0], and RXER.
In 10Mbps mode, RXC is recovered from the line while carrier is active. RXC is derived from the PHY’s reference
clock when the line is idle, or link is down.
In 100Mbps mode, RXC is continuously recovered from the line. If link is down, RXC is derived from the PHY’s
reference clock.
RXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
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