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参数资料
型号： KSZ8041NL-EVAL
厂商： Micrel Inc
文件页数： 19/54页
文件大小： 0K
描述： BOARD EVALUATION FOR KSZ8041NL
标准包装： 1
主要目的： 接口，以太网 PHY
嵌入式： 否
已用 IC / 零件： KSZ8041NL
主要属性： 单芯片 PHY，10BASE-T/100BASE-TX
次要属性： MII，RMII，HP 自动 MDI，MDI-X 自动极性校正
已供物品： 板
产品目录页面： 1114 (CN2011-ZH PDF)
相关产品： 576-3296-5-ND - IC TXRX PHY 10/100 AUTO 32-MLF
576-2109-6-ND - IC TXRX PHY 10/100 LV/LP 32-MLF
576-2109-1-ND - IC TXRX PHY 10/100 LV/LP 32-MLF
576-2109-2-ND - IC TXRX PHY 10/100 LV/LP 32-MLF
KSZ8041NLA3TR-ND - TRANSCEIVER 10/100 32-MLF
576-1645-6-ND - IC TXRX PHY 10/100 LV/LP 32-MLF
576-1645-1-ND - IC TXRX PHY 10/100 LV/LP 32-MLF
576-1645-2-ND - IC TXRX PHY 10/100 LV/LP 32-MLF
其它名称： 576-1621
Micrel, Inc.
KSZ8041NL/RNL
September 2010
26
M9999-090910-1.4
RMII Signal Definition
The Tables 3 and 4 describe the RMII signals for KSZ8041NL and KSZ8041RNL. Refer to RMII Specification for detailed
information.
RMII
Signal Name
Direction
(with respect to PHY,
KSZ8041NL signal)
Direction
(with respect to MAC)
Description
REF_CLK
Input
Input, or Output
Synchronous 50 MHz clock reference for
receive, transmit and control interface
TX_EN
Input
Output
Transmit Enable
TXD[1:0]
Input
Output
Transmit Data [1:0]
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data [1:0]
RX_ER
Output
Input, or (not required)
Receive Error
Table 3. RMII Signal Description – KSZ8041NL
RMII
Signal Name
Direction
(with respect to PHY,
KSZ8041RNL signal)
Direction
(with respect to MAC)
Description
REF_CLK
Output
Input
Synchronous 50 MHz clock reference for
receive, transmit and control interface
TX_EN
Input
Output
Transmit Enable
TXD[1:0]
Input
Output
Transmit Data [1:0]
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data [1:0]
RX_ER
Output
Input, or (not required)
Receive Error
Table 4. RMII Signal Description – KSZ8041RNL
Reference Clock (REF_CLK)
REF_CLK is a continuous 50MHz clock that provides the timing reference for TX_EN, TXD[1:0], CRS_DV, RXD[1:0], and
RX_ER.
The KSZ8041NL inputs the 50MHz REF_CLK from the MAC or system board.
The KSZ8041RNL generates the 50MHz RMII REF_CLK and outputs it to the MAC.
Transmit Enable (TX_EN)
TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all di-bits to be transmitted are presented on the RMII, and is negated
prior to the first REF_CLK following the final di-bit of a frame.
TX_EN transitions synchronously with respect to REF_CLK.
Transmit Data [1:0] (TXD[1:0])
TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for
transmission by the PHY. TXD[1:0] is ”00” to indicate idle when TX_EN is de-asserted. Values other than “00” on TXD[1:0]
while TX_EN is de-asserted are ignored by the PHY.
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相关代理商/技术参数
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