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参数资料
型号： KSZ8841-16MBL
厂商： Micrel Inc
文件页数： 66/105页
文件大小： 0K
描述： IC MAC CTLR 1PORT ETH 100-LBGA
标准包装： 260
控制器类型： 以太网控制器，MAC
接口： 总线
电源电压： 3.1 V ~ 3.5 V
工作温度： 0°C ~ 70°C
安装类型： 表面贴装
封装/外壳： 100-LBGA
供应商设备封装： 100-LFBGA
包装： 托盘
产品目录页面： 1080 (CN2011-ZH PDF)
其它名称： 576-3075
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
October 2007
63
M9999-102207-1.6
Bank 16 Transmit Control Register (0x00): TXCR
This register holds control information programmed by the CPU to control the QMU transmit module function.
Bit
Default Value
R/W
Description
15
-
RO
Reserved.
14-13
0x0
RW
Reserved.
12-4
-
RO
Reserved.
3
0x0
RW
TXFCE Transmit Flow Control Enable
When this bit is set and the KSZ8841M is in full-duplex mode, flow control is enabled. The
KSZ8841M transmits a PAUSE frame when the Receive Buffer capacity reaches a threshold
level that will cause the buffer to overflow.
When this bit is set and the KSZ8841M is in half-duplex mode, back-pressure flow control is
enabled. When this bit is cleared, no transmit flow control is enabled.
2
0x0
RW
TXPE Transmit Padding Enable
When this bit is set, the KSZ8841M automatically adds a padding field to a packet shorter than
64 bytes.
Note: Setting this bit requires enabling the add CRC feature to avoid CRC errors for the
transmit packet.
1
0x0
RW
TXCE Transmit CRC Enable
When this bit is set, the KSZ8841M automatically adds a CRC checksum field to the end of a
transmit frame.
0
0x0
RW
TXE Transmit Enable
When this bit is set, the transmit module is enabled and placed in a running state. When reset,
the transmit process is placed in the stopped state after the transmission of the current frame
is completed.
Bank 16 Transmit Status Register (0x02): TXSR
This register keeps the status of the last transmitted frame.
Bit
Default Value
R/W
Description
15
0x0
RO
Reserved.
14
0x0
RO
TXUR Transmit Underrun
This bit is set when underrun occurs.
Note: This is a fatal status. Software should guarantee that no underrun condition occurred
when enabling the early transmit function. The system or the QMU requires a reset or restart
to recover from an underrun condition.
To aviod transmit underun condition, the user has to make sure that the host interface speed
(bandwidth) is faster than the ethernet port.
13
0x0
RO
TXLC Transmit Late Collision
This bit is set when a transmit Late Collision occurs.
12
0x0
RO
TXMC Transmit Maximum Collision
This bit is set when a transmit Maximum Collision is reached.
11-6
-
RO
Reserved.
5-0
-
RO
TXFID Transmit Frame ID
This field identifies the transmitted frame. All of the transmit status information in this register
belongs to the frame with this ID.
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