参数资料
型号: KSZ8841-16MBL
厂商: Micrel Inc
文件页数: 76/105页
文件大小: 0K
描述: IC MAC CTLR 1PORT ETH 100-LBGA
标准包装: 260
控制器类型: 以太网控制器,MAC
接口: 总线
电源电压: 3.1 V ~ 3.5 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 100-LBGA
供应商设备封装: 100-LFBGA
包装: 托盘
产品目录页面: 1080 (CN2011-ZH PDF)
其它名称: 576-3075
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
October 2007
72
M9999-102207-1.6
Bank 19 Multicast Table Register 1 (0x02): MTR1
Multicast table register 1.
Bit
Default Value
R/W
Description
15-0
0x0
RW
MTR0 Multicast Table 1
When the appropriate bit is set, if the packet received with DA matches the CRC, the hashing
function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR, all
multicast addresses are received regardless of the multicast table value.
Bank 19 Multicast Table Register 2 (0x04): MTR2
Multicast table register 2.
Bit
Default Value
R/W
Description
15-0
0x0
RW
MTR0 Multicast Table 2
When the appropriate bit is set, if the packet received with DA matches the CRC, the hashing
function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR, all
multicast addresses are received regardless of the multicast table value.
Bank 19 Multicast Table Register 3 (0x06): MTR3
Multicast table register 3.
Bit
Default Value
R/W
Description
15-0
0x0
RW
MTR0 Multicast Table 3
When the appropriate bit is set, if the packet received with DA matches the CRC, the hashing
function is received without being filtered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXRA) or receive multicast (RXRM) bit is set in the RXCR, all
multicast addresses are received regardless of the multicast table value.
Bank 19 Power Management Control and Status Register (0x08): PMCS
The following control and status register provides information on the KSZ8841M power management capabilities. The
following table shows the register bit fields.
Bit
Default Value
R/W
Description
15
0
RO
(W1C)
PME_Status
This bit indicates that the KSZ8841M has detected a power-management event. If bit
PME_Enable is set, the KSZ8841M also asserts the PMEN pin. This bit is cleared on power-
up reset or by write 1. It is not modified by either hardware or software reset. When this bit is
cleared, the KSZ8841M deasserts the PMEN pin.
14-9
0x00
RO
Reserved.
8
0
RW
PME_Enable
If this bit is set, the KSZ8841M can assert the PMEN pin. Otherwise, assertion of the PMEN
pin is disabled.
This bit is cleared on power-up reset and will be not modified by software reset.
7-4
0x0
RO
Reserved.
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