
L99PM62XP
Description
Doc ID 16363 Rev 2
Note:
Inputs TxDL, TxDC and CSN must be at high level or at high impedance in order to achieve
minimum standby current in V1 standby mode.
Inputs DI and CLK must be at GND or at high impedance to achieve minimum standby
current in V1 standby mode.
Interrupt
The interrupt signal (linked to RxDL/NINT internally) indicates a wake-up event from V1
standby mode. In case of a wake-up by Wake-up Inputs, activity on LIN or CAN, SPI access
or timer-interrupt the NINT pin is pulled low for 56 s.
In case of V1 standby mode and (IV1 > Icmp), the device remains in standby mode, the V1
regulator switches to high current mode and the watchdog starts. No Interrupt signal is
generated.
2.2.4
VBAT standby mode
The transition from active mode to VBAT standby mode is initiated by an SPI command.
In VBAT standby mode, the V1 voltage regulator, relay outputs, LIN and CAN transmitters are
switched off. High-side outputs and the V2 regulator remain in the configuration
programmed prior to the standby command.
In VBAT standby mode the current consumption of the L99PM62XP is reduced to a minimum
level.
Note:
Inputs TXDL, TXDC and CSN must be terminated to GND in VBAT standby to achieve
minimum standby current.
This can be achieved with the internal ESD protection diodes of the microcontroller
(microcontroller is not supplied in this mode; V1 is pulled to GND).
2.2.5
Wake up from standby modes
A wake-up from standby mode switches the device to active mode. This can be initiated by
one or more of the following events:
Table 3.
Wake up sources
Wake up source
Description
LIN bus activity
Can be disabled by SPI
CAN bus activity
Can be disabled by SPI
Level change of WU1 - 3
Can be individually configured or disabled by SPI
IV1 > Icmp
Device remains in V1 standby mode but watchdog is enabled (If
Icmp = 0) and the V1 regulator goes into high current mode (increased
current consumption). No interrupt is generated.
Timer interrupt / wake up
of C by TIMER
Programmable by SPI
–V1 standby mode: device wakes up and Interrupt signal is generated
at RxDL/NINT when programmable timeout has elapsed
–VBAT standby mode: device wakes up, V1 regulator is turned on and
NReset signal is generated when programmable timeout has elapsed
SPI access
Always active (except in VBAT standby mode)
Wake up event: CSN is low and first rising edge on CLK