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Functional Description of the LB11875
1. Speed Control Circuit
Since the LB11875 adopts a PLL based speed control technique, it is able to provide high precision stable motor
speeds with low jitter. This PLL circuit compares the phases of the edges of the CLK signal (falling edges) and the
FG signal (falling edges on the FGIN+ and FGS output signals) and controls the motor speed based on the error
detected by that comparison.
The FG servo frequency during this control operation is determined by the formula shown below using the frequency
of the clock input (fCLK) and the divisor selected by the CLKSEL pin.
fFG (servo) = fCLK
÷ <divisor>
2. Output Drive Circuit
To minimize the power loss in the outputs, the LB11875 adopts a direct PWM drive technique. The (external) output
transistors operate in the saturated state when on, and the motor drive power is adjusted by changing the output on
duty.
The PWM switching is applied to the UH, VH, and WH outputs. Either high side or low side PWM switching can be
selected by changing the circuits with which the external transistors are connected.
3. Current Limiter Circuit
The current limiter circuit limits the (peak) current to a current determined by the equation I = VRF/Rf (VRF = 0.25
V (typical), Rf: the current detection resistor). The current limiter circuit reduces the output on duty to suppress the
current.
High precision current detection can be achieved in application circuits by making the wiring from the ends of the
current detection resistor (Rf) to the RF and RFGND pins as short as possible.
4. Reference Clock
Application must assure that no chattering or other noise occurs on the externally provided clock signal. Although the
input circuit does have hysteresis, insert a capacitor or other noise filter to remove noise if problems occur.
If the IC is set to the start state when no reference clock signal is input, the motor will turn a certain amount and then
the drive will be turned off.
5. PWM Frequency
The PWM frequency is determined by the capacitance of the capacitor C (F) connected to the PWM pin.
fPWM = 1/(30000 × C)
If a 620 pF capacitor is used, the frequency will be roughly 50 kHz. If the PWM frequency is too low, the motor
switching noise will be audible, and if too high, power loss in the output will be excessive. A frequency in the range
30 to 100 kHz is desirable. Lines that are as short as possible must be used for this capacitor to minimize the
susceptibility of this circuit to noise.
6. Hall Sensor Input Signals
To minimize the influence of noise and other problems, the Hall sensor input signals should have amplitudes of over
100 mV. If the output waveforms (at phase switching) are disrupted by noise, capacitors must be inserted across the
inputs to prevent that disruption.
If the outputs from a Hall sensor IC are input, hold one of the inputs (either the + or the - input) fixed at a voltage
within the common-mode input voltage range that applies when Hall sensors are used directly, and input the IC
output to the other input as a signal with the range 0 to VCC.
7. FG Input Signal
Normally, any one of the Hall signal input phases can be used as the FG signal input. If noise is a problem, add a
filter that consists of either a capacitor or a capacitor and a resistor.
No. 7678-13/16
LB11875