
8. Rotor Constraint Protection Circuit
The LB11875 includes a constraint protection circuit that protects the IC and the motor if the motor is physically
constrained. If the LD output remains high (indicating the unlocked state) for a certain fixed time with the IC in the
start state, this circuit turns off the PWM drive side output. The capacitance of the capacitor connected to the CSD
pin sets the time.
Set time (seconds) = 120 × C (F)
If a 0.068 F capacitor is used, the protection time will be approximately 8 seconds. The set time must be set to have
a margin larger than the motor startup time. This protection circuit will not operate when braking the motor by
switching the clock frequency. The IC must be set to the stop state, or power cut off and reapplied, to clear the
protection state.
Since the CSD pin also functions to generate the initial reset pulse, the logic circuit will remain in the reset state and
speed control will not be possible if the CSD pin is connected to ground. Therefore, if the constraint protection circuit
is not used, the CSD pin must be connected to ground by a resistor (about 220 k
) and capacitor (about 4700 pF)
connected in parallel.
9. Low-voltage Protection Circuit
The LB11875 includes an undervoltage protection circuit to prevent incorrect operation when power is first applied
and when the supply voltage drops. This circuit turns off the PWM drive side output when the LVSD pin voltage falls
below about 3.7 V (typical), and releases the protection state when the voltage rises about 4.2 V (typical). An
arbitrary operating voltage can be set by adding an external zener diode.
10. Phase Lock Signal
1. Phase lock range
Since the LB11875 does not have a counter or similar function in the speed system, the speed error range in the
phase locked state cannot be determined solely from the IC characteristics. (This is because the operation is
influenced by the acceleration of the change in the FG frequency.) If it is necessary to stipulate this for the motor,
then it will be necessary to determine this by actually measuring it in the motor state. Since speed errors occur
more easily in states with high FG acceleration, the speed error is thought to be the largest during lock pull in at
startup and in the unlocked state when switching the clock frequency.
2. Masking function for the phase lock state signal
The LB11875 can output the lock signal in a stable state by masking the short period low-level signals due to
hunting during lock pull in. However, the lock signal output is delayed by the amount of the mask time.
The mask time is set by the capacitance of the capacitor connected between the CLD pin and ground.
Mask time (seconds) = 0.9 × C (F)
If a 0.1 F capacitor is used, the mask time will be about 90 ms. If it is necessary to provide complete masking,
adequate margin must be provided in the mask time. Leave the CLD pin open if masking is not required.
11. Power Supply Stabilization
1. VCC
Since the LB11875 is used in switching drive applications with high output currents, the power supply line voltage
can be disrupted easily. Therefore, capacitors that are fully adequate for power supply stabilization must be
inserted between the VCC pin and ground. The capacitor ground must be located as close as possible to the IC
ground.
Since the power supply line is most easily disturbed during lock pull in at high motor speeds, operation in that state
must be analyzed carefully and capacitors with adequate capacitance selected.
The power supply voltage will be particularly susceptible to disruption if diodes are inserted in the power lines to
prevent damage if the power supply is connected with the polarity reversed. In this case, even larger capacitors
must be used.
No. 7678-14/16
LB11875
Continued on next page.