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参数资料
| 型号： | LC5512MB-45FN256C |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 10/99页 |
| 文件大小： | 0K |
| 描述： | IC CPLD 512MACROCELLS 256FPBGA |
| 标准包装： | 90 |
| 系列： | ispXPLD® 5000MB |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 4.5ns |
| 电压电源 - 内部： | 2.3 V ~ 2.7 V |
| 逻辑元件/逻辑块数目： | 16 |
| 宏单元数： | 512 |
| 输入/输出数： | 193 |
| 工作温度： | 0°C ~ 90°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BGA |
| 供应商设备封装： | 256-FPBGA（17x17） |
| 包装： | 托盘 |
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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
14
CAM Mode
In CAM Mode the multi-function array is configured as a Ternary Content Addressable Memory (CAM). CAM
behaves like a reverse memory where the input is data and the output is an address. It can be used to perform a
variety of high-performance look-up functions. As such, CAM has two modes of operation. In write or update mode
the CAM behaves as a RAM and data is written to the supplied address. In read or compare operations data is sup-
plied to the CAM and if this matches any of the data in the array the Match and Multiple Match (if there is more than
one match) flags are set to true and the lowest address with matching data is output. The CAM contains 128
entries of 48 bits. Figure 13 shows the block diagram of the CAM.
To further enhance the flexibility of the CAM a mask register is available. If enabled during updates, bits corre-
sponding with those set to 1 in the mask register are not updated. If enabled during compare operations, bits corre-
sponding to those set to 1 in the mask register are not included in the compare. A write don’t care signal allows
don’t cares to be programmed into the CAM if desired. Like other write operations the mask register controls this.
The write/comp data, write address, write enable, write chip select, and write don’t care signals are synchronous.
The CAM Output signals, match flag, and multimatch flag can be synchronous or asynchronous. The Enable mask
register input is not latched but must meet setup and hold times relative to the write clock. All inputs must use the
same clock and clock enable signals. All outputs must use the same clock and clock enable signals. Reset is com-
mon for both inputs and outputs. Table 9 shows the allowable sources for clock, clock enable, and reset for the var-
ious CAM registers.
Figure 13. CAM Mode
Table 9. Register Clocks, Clock Enables, and Initialization in CAM Mode
Register
Input
Source
Write data, Write address,
Enable mask register, Write
enable, write chip select, and
write don’t care, CAM Output,
Match, and Multimatch
Clock
CLK or one of the global clocks (CLK0 - CLK3). Each of these signals can
be inverted if required.
Clock Enable
WE or one of the global clocks (CLK1 - CLK 2). Each of these signals can
be inverted if required.
Reset
Created by the logical OR of the global reset signal and RST. RST is routed
by the multifunction array from GRP, with inversion if desired
‘
68 Inputs
From
Routing
Write Enable (WE)
En Mask Reg (EN_MASK)
Reset (RST)
Write Chip Sel (WCS[0:1])
CLK (CLK)
Clock Enable (CE)
Write/Comp Data
(WD[0:31])
128X48
CAM
Write Address
(WAD[0:6])
WR Mask Reg (WR_MASK)
WR don t care (WR_DC)
RESET
CLK0
CLK3
CLK1
CLK2
CAM
Output
CO[0:6]
Match
Out
MATCH
Multi-
match
Out
MUL_MATCH
SELECT
DEVICES
DISCONTINUED
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相关代理商/技术参数 |
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| LC5512MB-45FN256I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MB-45FN484C | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC5512MB-45FN484I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MB-45FN672C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MB-45FN672I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
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