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| 型号： | LC5512MB-45FN256C |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 49/99页 |
| 文件大小： | 0K |
| 描述： | IC CPLD 512MACROCELLS 256FPBGA |
| 标准包装： | 90 |
| 系列： | ispXPLD® 5000MB |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 4.5ns |
| 电压电源 - 内部： | 2.3 V ~ 2.7 V |
| 逻辑元件/逻辑块数目： | 16 |
| 宏单元数： | 512 |
| 输入/输出数： | 193 |
| 工作温度： | 0°C ~ 90°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BGA |
| 供应商设备封装： | 256-FPBGA（17x17） |
| 包装： | 托盘 |
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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
49
Signal Descriptions
Signal Names
Descriptions
TMS
Input – This pin is the Test Mode Select input, which is used to control the IEEE 1149.1
state machine.
TCK
Input – This pin is the Test Clock input pin, used to clock the IEEE 1149.1 state
machine.
TDI
Input – This pin is the IEEE 1149.1 Test Data in pin, used to load data.
TDO
Output – This pin is the IEEE 1149.1 Test Data out pin used to shift data out.
TOE
Input – Test Output Enable pin. TOE tristates all I/O pins when driven low.
GOE0, GOE1
Input – Global output enable inputs.
RESET
Input – This pin resets all the registers in the device. The global polarity for this pin is
selectable on a global basis. The default is active low. An external pull-down is
required when polarity is set to active high.
yzz
Input/Output – These are the general purpose I/O used by the logic array.
y is the MFB
reference (alpha) and z is the macrocell reference (numeric)
y: A-X (768 macrocells)
y: A-P (512 macrocells)
y: A-H (256 macrocells)
z: 0-31
GND
GND – Ground
NC
No connect
VCC
VCC – The power supply pins for core logic.
VCCO0, VCCO1, VCCO2, VCCO3
VCC – The power supply pins for I/O banks 0, 1, 2, and 3.
VREF0, VREF1, VREF2, VREF3
Input – This pin defines the reference voltage for I/O banks 0, 1, 2, and 3.
GCLK0, GCLK1, GCLK2, GCLK3
Input – Global clock/clock enable inputs (see Figure 14 for differential pairing).
CLK_OUT0, CLK_OUT1
Output – Optional clock output from PLL 0 and 1.
PLL_RST0, PLL_RST1
Input – Optional input resets the M divider in PLL 0 and 1.
PLL_FBK0, PLL_FBK1
Input – Optional feedback input for PLL 0 and 1.
GNDP
GND – Ground for PLLs.
VCCP
VCC – The power supply pin for PLLs.
VCCJ
VCC – The power supply for the IEEE 1149.1 interface.
DATA
x
I/O – sysCONFIG data pins, bit
x.
CSB
Input – sysCONFIG interface chip select. Drive low to select sysCONFIG interface.
CFG0
Input – Defines SRAM configuration mode. Low: sysCONFIG port, high: E
2CMOS or
IEEE 1149.1 TAP.
PROGRAMB
Input – Controls the programming of SRAM. Hold high for normal operation. Toggle low
to reload SRAM from E
2 memory.
CCLK
1
Input – Clock for sysCONFIG interface. Reads and writes occur on the rising edge of
the clock.
READ
1
Input – Drive high to perform reads from the sysCONFIG interface.
INITB
I/O – Indicates status of configuration. Can be driven low to inhibit configuration.
DONE
Output (open drain) – Indicates status of configuration.
1. These inputs should not toggle during power up for proper power-up configuration.
SELECT
DEVICES
DISCONTINUED
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LC5512MB-45FN256I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MB-45FN484C | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC5512MB-45FN484I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MB-45FN672C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MB-45FN672I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
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