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| 型号： | LC5512MC-75QN208I |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 中文描述： | EE PLD, 9.5 ns, PQFP208 |
| 封装： | LEAD FREE, PLASTIC, QFP-208 |
| 文件页数： | 2/95页 |
| 文件大小： | 923K |
| 代理商： | LC5512MC-75QN208I |
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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
10
True Dual-Port SRAM Mode
In Dual-Port SRAM Mode the multi-function array is configured as a dual port SRAM. In this mode two independent
read/write ports access the same 8,192-bits of memory. Data widths of 1, 2, 4, 8, and 16 are supported by the
MFB. Figure 9 shows the block diagram of the dual port SRAM.
Write data, address, chip select and read/write signals are always synchronous (registered.) The output data sig-
nals can be synchronous or asynchronous. Resets are asynchronous. All inputs on the same port share the same
clock, clock enable, and reset selections. All outputs on the same port share the same clock, clock enable, and
reset selections. Selections may be made independently between both inputs and outputs and ports. Table 5
shows the possible sources for the clock, clock enable and initialization signals for the various registers.
Figure 9. Dual-Port SRAM Block Diagram
Table 5. Register Clock, Clock Enable, and Reset in Dual-Port SRAM Mode
Register
Input
Source
Address, Write Data,
Read Data, Read/
Write, and Chip
Select
Clock
CLKA (CLKB) or one of the global clocks (CLK0 - CLK3). The selected sig-
nal can be inverted if desired.
Clock Enable
CENA (CENB) or one of the global clocks (CLK1 - CLK 2). The selected sig-
nal can be inverted if required.
Reset
Created by the logical OR of the global reset signal and RSTA (RSTB).
RSTA (RSTB) can be inverted is desired.
‘
Read/Write Address
(ADA[0:8-12])
Clock A (CLKA)
Write/Read A (WRA)
Reset A (RSTA)
68 Inputs
From
Routing
Dual
Port
SRAM
Array
PORT A
PORT B
Similar signals
as PORT A:
ADB[0:8-12], RSTB,
CLKB, CENB, WRB,
CSB[0,1], DIB[0:0,1,3,7,15]
Write Data
(DIA[0:0,1,3,7,15])
Chip Sel A (CSA [0:1])
Clk En A (CENA)
RESET
CLK0
CLK3
CLK1
CLK2
RD Data A
(DOA[0:0-15])
RD Data B
(DOB[0:0-15])
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相关代理商/技术参数 |
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| LC5512M-PAC-EV | 功能描述:可编程逻辑 IC 开发工具 Eval Board for XPLD5512 PAC1208 RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| LC5512MV-45F208C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MV-45F208I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MV-45F256C | 功能描述:CPLD - 复杂可编程逻辑器件 3.3V 193 I/O RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC5512MV-45F256I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
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