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参数资料
| 型号： | LC72134M |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 160 MHz, PDSO24 |
| 封装： | MFP-24 |
| 文件页数： | 25/27页 |
| 文件大小： | 463K |
| 代理商： | LC72134M |
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No. 5814-7/27
LC72134M
Continued from preceding page.
Pin
Pin No.
Type
Function
Equivalent circuit
IF counter 1
IFIN1 is selected when LCTS in the serial data is set to 0.
The input frequency range is 0.4 to 25 MHz when IFS is 1, and 0.4 to 12 MHz
when IFS is 0.
The signal is passed directly to the IF counter.
The result is output, MSB first, through the DO pin.
Four measurement periods are supported: 4, 8, 32, and 64 ms.
IFIN1
15
IF counter 2
input port
IFIN2 is selected when both LCTS and L/I1 in the serial data are set to 1.
The input frequency range is 0.4 to 25 MHz when IFS is 1 and 0.4 to 12 MHz
when IFS is 0.
The signal is passed directly to the IF counter.
The result (the IF counter value) is output, MSB first, through the DO pin.
Four measurement periods are supported: 4, 8, 32, and 64 ms.
If the L/I1 bit in the serial data is set to 0, the IFIN2/I1 port will function as an input
port and the state of the input pin will be reported to the microcontroller from the
DO pin. (Note that the LCTS value is ignored in this case.)
When the input state is low: the data will be 0:
When the input state is high: the data will be 1:
IFIN2/I1
13
Sub PLL local
oscillator
signal input
FMINb is selected when SDVS in the serial data is set to 1.
The input frequency range is 10 to 160 MHz.
The signal is passed through an internal divide-by-two prescaler and then input to
the swallow counter.
The divisor can be set to a value in the range 272 to 8191. Since the internal
divide-by-two prescaler is used, the actual divisor will be twice the set value.
FMINb goes to the stopped state (pulled down) when SDVS in the serial data is
set to 0.
FMINb
12
Sub PLL
charge pump
output
Sub PLL charge pump output
A high level is output from the PD pin when the frequency of the local oscillator
signal divided by N is higher than the reference frequency, and a low level is
output when that frequency is lower. This pin goes to the high-impedance state
when the frequencies match.
PDb
11
Sub PLL low-
pass filter
amplifier
transistor
Connections for the n-channel MOS transistor used for the sub PLL active low-
pass filter.
AINb
AOUTb
10
9
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LC72135M | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning |
| LC72135MA-AE | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| LC72135MA-Q-AE | 制造商:ON Semiconductor 功能描述:PLL FREQUENCY SYNTHESIZER - Tape and Reel 制造商:ON Semiconductor 功能描述:REEL / PLL FREQUENCY SYNTHESIZER |
| LC72135M-Q-TLM-E | 制造商:SANYO Semiconductor Co Ltd 功能描述: |
| LC72136 | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning |
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