- 您现在的位置：买卖IC网 > PDF目录97997 > LC72151V PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO30 PDF资料下载
参数资料
| 型号： | LC72151V |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO30 |
| 封装： | SSOP-30 |
| 文件页数： | 6/29页 |
| 文件大小： | 326K |
| 代理商： | LC72151V |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页
No. 6976-14/29
LC72151V
Continued from preceding page.
No.
Control block/data
Content
Related data
Width selection for the phase error (E) detection function used to determine the PLL
locked/unlocked state. When a phase error greater than the E detection width from the
table occurs, the PLL circuit is seen as in the unlocked state.
*: When unlocked, the DO pin goes low and the serial data output is UL = 0.
ULD
DT0, DT1
DVS
SNS
(9)
Unlock state detection data
UL0, UL1
Controls the phase comparator dead band.
*: The phase comparator operates in DZA mode after the power-on reset. (Recomended
modes: DZD, DZC)
(11)
Phase comparator control data
DZ0, DZ1
Bit that forcible sets the charge pump output to the low level.
DLC = 1: Low level
DLC = 0: Normal operation
*: If a deadlock occurs due to the VCO control voltage (Vtune) going to zero and stopping
the VCO oscillator, set the charge pump output to the low level and set Vtune to VCC to
escape from the deadlocked state (deadlock clearing circuit). Normal operation is
selected after the power-on reset.
(10)
Charge pump control data
DLC
Data to control the frequency in the convergence range to judge the high-speed locking
control completion. This data is valid when FMIN (high-speed mode) is selected by
setting DVS and SNS to 1.
*:The convergence range is 200 kHz at a power-on reset.
Refer to Description of the High-Speed Locking Control System (P.19) for details.
(12)
High-speed locking convergence
range control data
TLR0, TLR1
UL1
UL0
E detection width
Detection output
X’tal
0
Stopped
Open
10.25 M/10.35 MHz
0
1
0
Directly outputs E
10.25 M/10.35 MHz
±0.49 s
E is extended by
10.25 MHz
0.1 to 0.2 ms.
1
0
±0.49 s
E is extended by
10.35 MHz
0.11 to 0.22 ms.
(fr = 30/9/3 k)
±0.43 s
E is extended by
10.35 MHz (Other
0.1 to 0.2 ms.
than fr = 30/9/3 k)
±0.98 s
E is extended by
10.25 MHz
0.1 to 0.2 ms.
1
±0.97 s
E is extended by
10.35 MHz
0.11 to 0.22 ms.
(fr = 30/9/3 k)
±0.87 s
E is extended by
10.35 MHz (Other
0.1 to 0.2 ms.
than fr = 30/9/3 k)
0.1 to 0.22ms
E
DO
Extended
Unlock state output
DZ1
DZ0
Dead band mode
0
DZA
0
1
DZB
1
0
DZC
1
DZD
TLR1 TLR0
Convergence range [kHz]
0
50
0
1
100
1
0
150
1
200
Continued on next page.
相关PDF资料 |
PDF描述 |
|---|---|
| LC7216M | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20 |
| LCP-10G3A4EDR | FIBER OPTIC TRANSCEIVER, 840-860nm, 10312.5Mbps(Tx), 10312.5Mbps(Rx), SURFACE MOUNT, LC CONNECTOR |
| LCP-10G3A4EDRH | FIBER OPTIC TRANSCEIVER, 840-860nm, 10312.5Mbps(Tx), 10312.5Mbps(Rx), SURFACE MOUNT, LC CONNECTOR |
| LCP-10G3B4QDR | FIBER OPTIC TRANSCEIVER, 1260-1355nm, 10000Mbps(Tx), 10000Mbps(Rx), SURFACE MOUNT, LC CONNECTOR |
| LCP-10G3B4QDRT | FIBER OPTIC TRANSCEIVER, 1260-1355nm, 10000Mbps(Tx), 10000Mbps(Rx), SURFACE MOUNT, LC CONNECTOR |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LC72151VS-MPB-E | 制造商:ON Semiconductor 功能描述:PLL FREQUENCY SYNTHESIZER - Ammo Pack |
| LC72151VS-TRM-E | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| LC7215F | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:MW/LW PLL Frequency Synthesizers |
| LC7215FM | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:MW/LW PLL Frequency Synthesizers |
| LC7216M | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning |
发布紧急采购，3分钟左右您将得到回复。