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参数资料
| 型号： | LC78684NE |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封装： | 14 X 14 MM, QFP-80 |
| 文件页数： | 13/24页 |
| 文件大小： | 177K |
| 代理商： | LC78684NE |
No. 7695-20/24
LC78684NE
Continued from preceding page.
Block
No.
Pin
I/O
Supplement
53
MADRS7
O
DRAM address output 7
54
MADRS6
O
DRAM address output 6
55
MADRS5
O
DRAM address output 5
Memory interface
56
MADRS4
O
DRAM address output 4
57
MADRS3
O
DRAM address output 3
58
MADRS2
O
DRAM address output 2
59
MADRS1
O
DRAM address output 1
60
MADRS0
O
DRAM address output 0
Power supply
61
DVDD5
—
Internal logic system power supply
62
VSS
—
Ground
When EDO DRAM is used: MP3 data request flag output (active high)/DRAM data request flag
MP3 stream
63
STREQ
I/O
input (in CD ROM mode: active high)
When SDRAM is used: CKE output (active low)
64
STCK
I/O
When EDO DRAM is used: MP3 data transfer clock input/DRAM data transfer clock output
I/O
When SDRAM is used: DQML output (active low)
65
STDAT
I/O
When EDO DRAM is used: MP3 data serial input/DRAM data serial output
When SDRAM is used: DQMH output (active low)
MP3 decoder
66
FSYNC
O
MP3 frame sync signal (active high)
Data continuity point detection complete flag (CD-DA mode, active high)
When EDO DRAM is used: CRC check (CD ROM data/CD-DA subcode data) result output (active
CD monitor
67
CRCF
O
high)/DRAM data output enable flag (active high)
When SDRAM is used: ADRS13 output
Power supply
68
DVDD6
—
Digital system power supply (I/O)
69
VSS
—
Ground
70
WOK
I
DRAM write enable input (CD-DA mode, active high)
DRAM data request flag input (only when EDO DRAM is used)
Data continuity point detection complete flag (CD-DA mode, active high)
Anti-shock/MP3 I/O
71
CNTOK
O
SYNC error monitor flag (MP3 mode, active high)
DRAM data serial output (only when EDO DRAM is used:)
DRAM write interrupted flag (CD-DA mode, active high)
72
OVF
O
Emphasis output flag (CD-DA and MP3 modes, active high)
DRAM data transfer clock output (only when EDO DRAM is used)
73
CMDOUT
O
Command serial data output (This is an n-channel open-drain output.)
74
CMDIN
I
Command serial data input
Microcontroller
75
CL
I
Command serial clock input
interface
76
CE
I
Command enable input (active high)
77
INTB
O
Interrupt signal output (active low)
DRAM write interrupted flag (CD-DA mode, active high)
78
RESB
I
System reset (active low)
CD IF
79
DATAIN
I
CD serial data input
80
DATACK
I
CD bit clock input
Note: 1. Notes on unused ports
Unused input pins must be connected to ground (0 V).
Unused output pins must be left open. Do not connect anything to these pins.
Unused I/O pins must either be connected to ground (0 V) or be left open.
2. The same potential must be supplied to all of the DVDD1, DVDD3, DVDD4, DVDD6, and AVDD pins. The same potential must also be supplied to
the DVDD2 and DVDD5 pins.
(See the Allowable Operating Ranges section for details on the voltage supplied.)
3. The input pins TEST1 and TEST2 must be connected to ground (0 V).
4. The I/O pins (MDATA0 to MDATA15, STREQ, STCK, and STDAT) are set to input mode by the initial system reset.
5. Applications must apply a low level (of at least 1 s) to the RESB after power is first applied.
6. A clock signal with a frequency of 16.9344 MHz must applied to the CKIN pin from the CD DSP IC or other source.
An oscillator circuit cannot be formed with just this IC and an oscillator element.
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相关代理商/技术参数 |
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| LC7868E | 制造商:SANYO 制造商全称:Sanyo Semicon Device 功能描述:Digital Signal Processor for Compact Disc Players |
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