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参数资料
| 型号： | LC78684NE |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封装： | 14 X 14 MM, QFP-80 |
| 文件页数： | 8/24页 |
| 文件大小： | 177K |
| 代理商： | LC78684NE |
No. 7695-16/24
LC78684NE
Data Serial I/O Interface
DRAM Data Serial Output Timing
*: When EDO DRAM is used, a transfer data command from DRAM must be issued first to output data from
DRAM. (This function cannot be used with SDRAM.)
If this command has not been issued, the clock and data signals will not be output from the STCK and
STDAT pins even if STREQ is set high.
T6
T5
T3
STDAT
STCK
T1
T2
Fsck
T4
STREQ
STCK
STDAT
CRCF
T7
Symbol
Parameter
Ratings
Unit
min
typ
max
Fsck
Transfer clock frequency
4.2336
MHz
T1
STDAT/STCK setup time
30
ns
T2
STDAT/STCK hold time
30
ns
T3
Data (1 byte) transfer time
1.89
s
T4
Data transfer wait time
1.89
s
T5
Data transfer start time
1.89
15.2
s
T6
Data transfer stop time
0
15.2
s
T7
Enable flag turn off time
210
236.2
270
ns
*1: The typical values apply when the frequency of the clock signal input to the CKIN pin is 16.9344 MHz.
*2: There are cases in data transfer operations where between a minimum of 0 bytes and a maximum of 4 bytes of data
are output from the STDAT pin after the STREQ pin goes low. The period T6 in the figure above stipulates this time.
*3: The T7 stipulation in the figure above applies when one or more bytes of data are output from the STDAT pin after
the STREQ pin goes low. The timing with which the CRCF pin goes low when data output from the STDAT does not
occur is the same as the timing with which STREQ goes low.
The Fsck clock frequency can also be set to 2.1168 MHz (typical), 1.084 MHz (typical).
In these cases, the values for T3 to T7 will be 2 times or 4 times the listed values.
The WOK, OVF, and CNTOK pins can be used in place of STREQ (input mode), STCK, and STDAT. The above
timing specifications apply in this case as well.
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