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参数资料
| 型号： | LC78684NE |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封装： | 14 X 14 MM, QFP-80 |
| 文件页数： | 9/24页 |
| 文件大小： | 177K |
| 代理商： | LC78684NE |
No. 7695-17/24
LC78684NE
MP3 Data Serial Input Timing
*: For data serial input, if EDO DRAM is used, a serial input command must have been issued. (This function
cannot be used with SDRAM.)
If this command has not been issued, the MP3 decoder will not operate, even if clock and data signals are
input to the STCK and STDAT pins.
STREQ
(*Output from the LC78684)
STDAT
STCK
T2
T3
T1h
T1l
Fsck
STCK
STDAT
Symbol
Parameter
Ratings
Unit
min
typ
max
Fsck
Transfer clock frequency *
9.216
MHz
T1h
STCK high-level pulse width
45
ns
T1l
STCK low-level pulse width
45
ns
T2
STDAT / STCK setup time
30
ns
T3
STDAT / STCK hold time
30
ns
Symbol
Parameter
Ratings
Unit
min
typ
max
Fsck
Transfer clock frequency
3.072
MHz
T1h
STCK high-level pulse width
150
ns
T1l
STCK low-level pulse width
150
ns
T2
STDAT / STCK setup time
125
ns
T3
STDAT / STCK hold time
125
ns
*: The maximum frequencies of the transfer clock signal during serial input are listed in the following table.
Determine the frequency of the transfer clock such that the frequency is below the maximum frequency listed above and the MP3 decoding processing is
performed in time.
Note that the values in the table above apply when MP3DSET (bit 0 in register 41h) is set to 1 (high-speed transfer
mode).
If MP3DSET is set to 0 (low-speed transfer mode) the following timings apply.
*2: The LC78684NE can receive up to a maximum of 3 bytes of data even after the STREQ pin has gone low.
MODE
Fs (KHz)
Maximum serial transfer clock frequency (MHz)
48
9.216
MPEG1
44.1
8.4672
32
6.144
MPEG2
24 (12)
4.608
(MPEG2.5)
22.05 (11.025)
4.2336
16 (8)
3.072
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