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参数资料
| 型号： | LC78684NE |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封装： | 14 X 14 MM, QFP-80 |
| 文件页数： | 4/24页 |
| 文件大小： | 177K |
| 代理商： | LC78684NE |
No. 7695-12/24
LC78684NE
Refresh Cycle (Auto Refresh)
MA[13:0]
MD[15:0]
T16
T15
CS
DCLK
CKE
WEB
DQMU
DQML
RASB
CASB
*: The correspondence between the signal names used in the above diagrams (Read Cycle, Write Cycle, and Refresh
Cycle) and the actual LC78684NE pin names is shown in the table below.
Signal name in figure
LC78684NE pin
Signal name in figure
LC78684NE pin
CS
OEB
MA [13]
CRCF
SDCLK
CASLB
MA [12:0]
MADRS [12:0]
CKE
STREQ
MD [15:0]
MDAT [15:0]
RASB
DQMU
STDAT
CASB
CASUB
DQML
STCK
WEB
Symbol
Parameter
Ratings
Unit
min
typ
max
T1
SDRAM clock frequency
59
ns
T2
Active to active command period
(T1)
× 6
—
ns
T3
Active to precharge command period (RAS to CAS delay)
(T1)
× 4
—
ns
T4
Active to read or write delay
(T1)
× 2
—
ns
T5
Command low-level width (CKE, RAS, CAS, WEB)
40
—
ns
T6
Command setup time (CKE, RAS, CAS, WEB, DQMU/L)
30
—
ns
T7
Command hold time (CKE, RAS, CAS, WEB, DQMU/L)
2.5
—
ns
T8
Address setup time
30
—
ns
T9
Address hold time
2.5
—
ns
T10
READ data setup time (DRAM: read / LC78684: input)
30
—
ns
T11
READ data hold time (DRAM: read / LC78684: input)
0
—
ns
T12
DQM low-level width (Bite-access mode)
90
—
ns
T13
WRITE data setup time (DRAM: write / LC78684E: output)
80
—
ns
T14
WRITE data hold time (DRAM: write / L78684E output)
2.5
—
ns
T15
Precharge to refresh command period
(T1)
× 2
—
ns
T16
Refresh to active command period
(T1)
× 6
—
ns
Notes: 1. These values apply when the frequency of the clock input to the CKIN pin is 16.9344 MHz.
2. The setup time and hold time values shown above are times relative to the rise of the SDCLK signal.
3. The above times are common to all of the read, write and refresh operation modes.
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