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参数资料
| 型号： | LCK4801 |
| 英文描述： | Low-Voltage HSTL Differential Clock |
| 中文描述： | 低电压差分HSTL时钟 |
| 文件页数： | 4/10页 |
| 文件大小： | 160K |
| 代理商： | LCK4801 |
Agere Systems Inc.
3
Preliminary Data Sheet
July 2001
Low-Voltage HSTL Differential Clock
LCK4801
Pin Information
Table 1. Pin Description
Pin Number
Pin Name
I/O1
Type
Description
1VDDD
P
Power Supply
3.3 V power supply.
2TESTM
I
LVCMOS
M divider test pins.
3VSS
G
Ground
Digital ground.
4
PCLK0_EN
I
LVCMOS
PCLK0 enable.
5
PCLK1_EN
I
LVCMOS
PCLK1 enable.
6
REF_SEL
I
LVCMOS
Selects the PLL input reference clock.
7
HSTL_CLK
I
Differential HSTL
PLL reference clock input.
8HSTL_CLK
I
Differential HSTL
PLL reference clock input.
9
PECL_CLK
I
Differential LVPECL
PLL reference clock input.
10
PECL_CLK
I
Differential LVPECL
PLL reference clock input.
11
EXTFB_EN
I
LVCMOS
External feedback enable.
12
EXTFB_IN
I
Differential HSTL
External feedback input.
13
EXTFB_IN
I
Differential HSTL
External feedback input.
14
VDDHSTL
P
Power Supply
Output buffers power supply.
15
EXTFB_OUT
O
Differential HSTL
External feedback output clock.
16
EXTFB_OUT
O
Differential HSTL
External feedback output clock.
17
VDDHSTL
P
Power Supply
Output buffers power supply.
18
PCLK1
O
Differential HSTL
Output clock 1.
19
PCLK1
O
Differential HSTL
Output clock 1.
20
PCLK0
O
Differential HSTL
Output clock 0.
21
PCLK0
O
Differential HSTL
Output clock 0.
22
VDDHSTL
P
Power Supply
Output buffers power supply.
23
PLLREF_EN
I
LVCMOS
PLL reference enable.
24
PLL_BYPASS
I
LVCMOS
Input signal PLL bypass.
25
VSS
P
Ground
Analog ground for PLL.
26
RESET
I
LVCMOS
PLL bypass reset (for test use).
27
SEL[4]
I
LVCMOS
Selection of input and feedback frequency.
28
SEL[3]
I
LVCMOS
Selection of input and feedback frequency.
29
SEL[2]
I
LVCMOS
Selection of input and feedback frequency.
30
SEL[1]
I
LVCMOS
Selection of input and feedback frequency.
31
SEL[0]
I
LVCMOS
Selection of input and feedback frequency.
32
VDDA
P
Power Supply
3.3 V filtered for PLL (PLL power supply).
1. P = power, I = input, G = ground, O = output.
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