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参数资料
| 型号： | LCK4801 |
| 英文描述： | Low-Voltage HSTL Differential Clock |
| 中文描述： | 低电压差分HSTL时钟 |
| 文件页数： | 6/10页 |
| 文件大小： | 160K |
| 代理商： | LCK4801 |
Agere Systems Inc.
5
Preliminary Data Sheet
July 2001
Low-Voltage HSTL Differential Clock
LCK4801
Pin Information (continued)
Table 3. Function Control
Absolute Maximum Characteristics
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for
extended periods can adversely affect device reliability.
Table 4. Absolute Maximum Ratings
Control Pin
0
1
REF_SEL
HSTL_CLK.
PECL_CLK.
TESTM
M divider test mode enabled.
Reference fed to bypass MUX.
PLLREF_EN
Disable the input to the PLL and reset
the M divider.
Enable the input to the PLL.
PLL_BYPASS
Outputs fed by input reference or M
divider.
Outputs fed by VCO.
EXTFB_EN
External feedback enabled.
Internal feedback enabled.
PCLK0_EN
PCLK0 = low, PCLK0 = high.
PCLK0 = high, PCLK0 = low.
PCLK1_EN
PCLK1 = low, PCLK1 = high.
PCLK1 = high, PCLK1 = low.
RESET
Resets feedback N divider.
Feedback enabled.
SEL[4:0]
Parameter
Symbol
Min
Typical
Max
Unit
Power Supply
VDDD/VDDA
–0.5
—
4.4
V
VDDHSTL
–0.5
—
4.4
Input Voltage
VIN
–0.5
—
VDDD + 0.3
V
Write Current
IIN
–1
—
1
mA
Storage Temperature
TS
–50
—
150
°C
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