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参数资料
| 型号： | LCK4801 |
| 英文描述： | Low-Voltage HSTL Differential Clock |
| 中文描述： | 低电压差分HSTL时钟 |
| 文件页数： | 8/10页 |
| 文件大小： | 160K |
| 代理商： | LCK4801 |
Agere Systems Inc.
7
Preliminary Data Sheet
July 2001
Low-Voltage HSTL Differential Clock
LCK4801
Electrical Characteristics (continued)
Table 6. ac Characteristics
VDDA = VDDD = 3.3 V ± 5%, VDDHSTL = 1.7 V—2.1 V, TA = 0 °C—70 °C.
2276 (F)
Figure 3. HSTL Differential Input Levels
2277 (F)
Figure 4. Output Termination and ac Test Reference
Symbol
Description
Min
Typ
Max
Unit
Condition
fref
Input Frequency
—
70—125
—
MHz
—
fMAX
Maximum Output
Frequency
336
—
1000
MHZ
—1
1. When the phase-locked loop is active but in bypass mode, fref maximum is limited by input the buffer; optimum performance is obtained
from PECL input.
tsk (o)
Skew Error (PCLK)
—
35
ps
—2
2. At differential pair crossover.
tjit (0)
Phase Jitter (I/O Jitter)
—
(output period)/2
—
—2
tjit (cc)
Cycle-to-Cycle Jitter
(Full Period)
——
5
%
—2,3
3. Full PCLK period.
tjit (1/2 period) Cycle-to-Cycle Jitter
(Half Period)
——
8
%
—2,
4
4. Half PCLK period.
VDIFout
Differential Output
Peak-to-Peak Swing
0.6
—
V
For all HSTL
output pairs.
VX
Differential Output
Crosspoint Voltage
0.68
—
0.9
V
For all HSTL
output pairs.
tlock
Maximum PLL Lock Time
—
10
ms
—
VDIF
VCM
VDDHSTL
VOH
VX
VOL
VSS
OUTPUT
Z = 50
VTT = VSS (GROUND)
RT = 25
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