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参数资料
| 型号： | lCL8052CDD |
| 厂商： | Intersil Corporation |
| 英文描述： | Precision 4 1/2 Digit, A/D Converter |
| 中文描述： | 精密4 1 / 2位，A / D转换 |
| 文件页数： | 8/19页 |
| 文件大小： | 168K |
| 代理商： | LCL8052CDD |
3-41
Zero-Crossing Flip-Flop
Figure 4 shows the problem that the zero-crossing F/F is
designated to solve.
The integrator output is approaching the zero-crossing point
where the count will be latched and the reading displayed.
For a 20,000 count instrument, the ramp is changing
approximately 0.50mV per clock pulse (10V Max integrator
output divided by 20,000 counts). The clock pulse
feedthrough superimposed upon this ramp would have to be
less than 100mV peak to avoid causing significant errors.
The flip-flop interrogates the data once every clock pulse
after the transients of the previous clock pulse and half-clock
pulse have died down. False zero-crossings caused by clock
pulses are not recognized. Of course, the flip-flop delays the
true zero-crossing by one count in every instance, and if a
correction were not made, the display would always be one
count too high. Therefore, the counter is disabled for one
clock pulse at the beginning of phase 3. This one count
delay compensates for the delay of the zero crossing flip-
flop, and allows the correct number to be latched into the
display. Similarly, a one count delay at the beginning of
phase 1 gives an overload display of 0000 instead of 0001.
No delay occurs during phase 2, so that true ratiometric
readings result.
Detailed Description
DIGITAL SECTION
The 71C03 includes several pins which allow it to operate
conveniently in more sophisticated systems. These include:
4-1/2 / 3-1/2 (Pin 2)
When high (or open) the internal counter operates as a full
4
1
/
2
decade counter, with a complete measurement cycle
requiring 40,002 counts. When held low, the least significant
decade is cleared and the clock is fed directly into the next
decade. A measurement cycle now requires only 4,0002
clock pulses. All 5 digit drivers are active in either case, with
each digit lasting 200 counts with Pin 2 high (4
1
/
2
digit) and
20 counts for Pin 2 low (3
1
/
2
digit).
RUN/HOLD (Pin 4)
When high (or open) the A/D will free-run with equally
spaced measurement cycles every 40,0002/4,002 clock
pulses. If taken low, the converter will continue the full mea-
surement cycle that it is doing and then hold this reading as
long as Pin 4 is held low. A short positive pulse (greater then
300ns) will now initiate a new measurement cycle beginning
with up to 10,001/1,001 counts of auto zero. Of course if the
pulse
occurs
before
the
(40,002/4,002 counts) is completed, it will not be recognized
and the converter will simply complete the measurement it is
doing. An external indication that full measurement cycle
has been completed is that the first STROBE pulse (see
below) will occur 101/11 counts after the end of this cycle.
Thus, if RUN/HOLD is low and has been low for at least
101/11 counts, converter is holding and ready to start a new
measurement when pulsed high.
full
measurement
cycle
STROBE (Pin 18)
This is a negative-going output pulse that aids in transferring
the BCD data to external latches, UARTs or microproces-
sors. There are 5 negative-going STROBE pulses that occur
COUNTS
PHASE I
PHASE II
PHASE III
4
1
/
2
DIGIT
3
1
/
2
DIGIT
10,001
10,000
20,001
1,001
1,000
2,001
FIGURE 3. CONVERSION TIMING
POLARITY
DETECTED
ZERO CROSSING
OCCURS
ZERO CROSSING
DETECTED
DEINT PHASE III
INT PHASE II
AZ PHASE I
AZ
INTEGRATOR
OUTPUT
CLOCK
INTERNAL LATCH
BUSY OUTPUT
NUMBER OF COUNTS TO ZERO CROSSING
PROPORTIONAL TO V
IN
AFTER ZERO CROSSING,
ANALOG SECTION WILL
BE IN AUTOZERO
CONFIGURATION
FIGURE 4. INTEGRATOR OUTPUT NEAR ZERO-CROSSING
TRUE ZERO
CROSSING
CLOCK
PULSE
FEEDTHROUGH
FALSE ZERO
CROSSING
ICL8052/ICL71C03, ICL8068/ICL71C03
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