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参数资料
| 型号： | LCMXO2280C-B-EVN |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 18/88页 |
| 文件大小： | 0K |
| 描述： | BOARD BREAKOUT MACHXO |
| 标准包装： | 1 |
| 系列： | MachXO |
| 主要目的： | * |
| 嵌入式： | * |
| 已用 IC / 零件： | * |
| 主要属性： | * |
| 次要属性： | * |
| 已供物品： | * |
| 其它名称： | 220-1149 |
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Architecture
MachXO Family Data Sheet
output data signals are multiplexed and provide a single signal to the I/O pin via the sysIO buffer. Figure 2-17
shows the MachXO PIO logic.
The tristate control signal is multiplexed from the output data signals and their complements. In addition a global
signal (TSALL) from a dedicated pad can be used to tristate the sysIO buffer.
The PIO receives an input signal from the pin via the sysIO buffer and provides this signal to the core of the device.
In addition there are programmable elements that can be utilized by the design tools to avoid positive hold times.
Figure 2-17. MachXO PIO Block Diagram
From Routing
From Routing
TS
sysIO
TSALL
TO
Buffer
Fast Output
Data signal
DO
PAD
1
Input
Data Signal
Programmable
Delay Elements
2
3
+
4 -
Note: Buffer 1 tracks with V CCAUX
Buffer 2 tracks with V CCIO.
Buffer 3 tracks with internal 1.2V V REF.
Buffer 4 is available in MachXO1200 and MachXO2280 devices only.
From Complementary
Pad
sysIO Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as Banks. The sysIO buffers allow users to implement the wide variety
of standards that are found in today’s systems including LVCMOS, TTL, BLVDS, LVDS and LVPECL.
In the MachXO devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are pow-
ered using V CCIO . In addition to the Bank V CCIO supplies, the MachXO devices have a V CC core logic power supply,
and a V CCAUX supply that powers up a variety of internal circuits including all the differential and referenced input buf-
fers.
MachXO256 and MachXO640 devices contain single-ended input buffers and single-ended output buffers with
complementary outputs on all the I/O Banks.
MachXO1200 and MachXO2280 devices contain two types of sysIO buffer pairs.
1. Top and Bottom sysIO Buffer Pairs ?
The sysIO buffer pairs in the top and bottom Banks of the device consist of two single-ended output drivers and
two sets of single-ended input buffers (for ratioed or absolute input levels). The I/O pairs on the top and bottom
2-15
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相关代理商/技术参数 |
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|---|---|
| LCMXO2280C-C-EVN | 功能描述:可编程逻辑 IC 开发工具 MACHXO CNRL EVB RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| LCMXO2280C-L-EV | 功能描述:可编程逻辑 IC 开发工具 MachXO 2280C Eval Br d - Standard RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| LCMXO2280C-M-EVN | 功能描述:可编程逻辑 IC 开发工具 MachXO Mini Dev Kit RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| LCMXO2280E-3B256C | 功能描述:CPLD - 复杂可编程逻辑器件 2280 LUTs 211 I/O 1.2V -3 SPD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LCMXO2280E-3B256I | 功能描述:CPLD - 复杂可编程逻辑器件 2280 LUTs 211 I/O 1.2V -3 SPD RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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