参数资料
型号: LCMXO2280C-B-EVN
厂商: Lattice Semiconductor Corporation
文件页数: 7/88页
文件大小: 0K
描述: BOARD BREAKOUT MACHXO
标准包装: 1
系列: MachXO
主要目的: *
嵌入式: *
已用 IC / 零件: *
主要属性: *
次要属性: *
已供物品: *
其它名称: 220-1149
Architecture
MachXO Family Data Sheet
There are 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent Slice/PFU).
There are 7 outputs: 6 to the routing and one to the carry-chain (to the adjacent Slice/PFU). Table 2-1 lists the sig-
nals associated with each Slice.
Figure 2-5. Slice Diagram
To Adjacent Slice/PFU
Slice
OFX1
A1
B1
C1
D1
CO
LUT4 &
CARRY
F
SUM
D
FF/
F1
Fast Connection
to I/O Cell*
Latch
Q1
From
Routing
M1
M0
CI
LUT
OFX0
To
Routing
A0
CO
Expansion
Mux
Fast Connection
to I/O Cell*
B0
C0
D0
LUT4 &
CARRY
CI
F
SUM
OFX0
D
FF/
Latch
F0
Q0
Control Signals
selected and
inverted per
Slice in routing
CE
CLK
LSR
From Adjacent Slice/PFU
Notes:
Some inter-Slice signals are not shown.
* Only PFUs at the edges have fast connections to the I/O cell.
Table 2-1. Slice Signal Descriptions
Function
Input
Input
Type
Data signal
Data signal
Signal Names
A0, B0, C0, D0 Inputs to LUT4
A1, B1, C1, D1 Inputs to LUT4
Description
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Multi-purpose
Control signal
Control signal
Control signal
Inter-PFU signal
Data signals
Data signals
Data signals
Data signals
Inter-PFU signal
M0/M1
CE
LSR
CLK
FCIN
F0, F1
Q0, Q1
OFX0
OFX1
FCO
Multipurpose Input
Clock Enable
Local Set/Reset
System Clock
Fast Carry In 1
LUT4 output register bypass signals
Register Outputs
Output of a LUT5 MUX
Output of a LUT6, LUT7, LUT8 2 MUX depending on the Slice
Fast Carry Out 1
1. See Figure 2-4 for connection details.
2. Requires two PFUs.
2-4
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