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参数资料
| 型号： | LE25CA322TT |
| 厂商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分类： | PROM |
| 英文描述： | 4K X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封装： | 0.150 INCH, MSOP-8 |
| 文件页数： | 13/14页 |
| 文件大小： | 217K |
| 代理商： | LE25CA322TT |
LE25CA322
No.NA1678-8/14
Description of Commands and Their Operations
“Table 1 Command Settings” provides a list and overview of the commands. A detailed description of the functions and
operations corresponding to each command is presented below.
1. Read (READ)
Consisting of the first through fourth bus cycles, the read command inputs the 16-bit addresses following (03h), and the
data in the designated addresses is output synchronized to SCK. The data is output from SO on the falling edge of
fourth bus cycle bit0 as a reference. “Figure 4 READ” shows the timing waveforms.
When SCK is input continuously after the read command has been input and the data in the designated addresses has
been output, the address is automatically incremented inside the device while SCK is being input, and the
corresponding data is output in sequence. If the SCK input is continued after the internal address arrives at the highest
address, the internal address returns to the lowest address (0000h), and data output is continued. By setting the logic
level of CS to high, the device is deselected, and the read cycle ends. While the device is deselected, the output pin SO
is in a high-impedance state.
Figure 4 READ
CS
SCK
SI
SO
Mode3
High Impedance
8CLK
Mode0
0 1
2 3 4 5
6
7 8
15 16
Add.
(00000011)
Add.
23 24 25 26 27 28 29 30 31
7
654
Data Out(N)
Data Out(N+1)
32 10 7
03h
(A15-A8)
(A7-A0)
Addresses A15 to A12 are “don’t care.”
In synchronization with the rising edges of 0 to 23 clock signals, the command is identified and the addresses are
taken in through SI.
In synchronization with the falling edges of 23 clock signal or later, the data is output to SO.
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