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参数资料
| 型号： | LE25CA322TT |
| 厂商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分类： | PROM |
| 英文描述： | 4K X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封装： | 0.150 INCH, MSOP-8 |
| 文件页数： | 5/14页 |
| 文件大小： | 217K |
| 代理商： | LE25CA322TT |
LE25CA322
No.NA1678-13/14
8. Software Data Protection
This product eliminates the possibility of unintentional operations by not recognizing commands under the following
conditions.
When a write command is input and the rising CS edge timing is not in a bus cycle (8CLK units of SCK).
When the write data is not in 1-byte increments.
When the status register write command is input for 2bus cycles or more.
9. Power-on
In order to protect against unintentional writing, CS must be kept at VDD at power-on. After power-on, the supply
voltage has stabilized at 2.7V or higher, wait for 10
μs (tPU_READ) before inputting the command to start a read
operation. Similarly, wait for 10ms (tPU_WRITE) after the supply voltage has stabilized at 2.7V or higher before
inputting the command to start a write operation.
10. Decoupling Capacitor
A0.1
μF ceramic capacitor must be provided to each device and connected between VDD and VSS in order to ensure
that the device will operate stably.
Figure 11 Status Register Write Flowchart
Figure 12 Write Flowchart
Status register write
Set status register
write command
Set write enable
command
Start
05h
Program start on
rising edge of CS
End of status
register write
YES
Bit 0= “0” ?
06h
01h
NO
*Automatically placed in write
disabled state at the end of the
status register write.
Data
Set status register
read command
Write
Start
05h
Set write command
Address 1
Address 2
Write start on rising
edge of CS
End of write
YES
Bit 0= “0” ?
Data 0
06h
Set write enable
command
02h
NO
Data 1
Data n
*Automatically placed
in write disabled state
at the end of the write.
Set status register
read command
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