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参数资料
| 型号： | LF3310QC12 |
| 厂商： | LOGIC DEVICES INC |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | Horizontal / Vertical Digital Image Filter |
| 中文描述： | 12-BIT, DSP-DIGITAL FILTER, PQFP144 |
| 封装： | PLASTIC, QFP-144 |
| 文件页数： | 10/21页 |
| 文件大小： | 287K |
| 代理商： | LF3310QC12 |
DEVICES INCORPORATED
LF3310
Horizontal / Vertical Digital Image Filter
10
Video Imaging Products
11/08/2001-LDS.3310-H
changed every clock cycle. This is
useful when filtering interleaved
data. When loading limit values into
the device, the upper limit must be
greater than the lower limit. Limit
register loading is discussed in the LF
Interface
TM
section.
V ertical Filter
The vertical filter is designed to filter
a digital image in the vertical dimen-
sion. It is a FIR filter which can be
configured to have as many as 8-taps.
Line Buffers
There are seven on-chip line buffers.
The maximum delay length of each
line buffer is 3076 cycles and the
minimum is 4 cycles. Configuration
Register 2 (CR
2
) determines the delay
length of the line buffers. The line
buffer length is equal to the value of
CR
2
plus 4. A value of 0 for CR
2
sets
the line buffer length to 4. A value of
3072 for CR
2
sets the line buffer
length to 3076. Any values for CR
2
greater than 3072 are not valid.
The line buffers have two modes of
operation: delay mode and recirculate
mode. Bit 0 of Configuration Register
3 determines which mode the line
buffers are in. In delay mode, the
data input to the line buffer is delayed
by an amount determined by CR
2
. In
recirculate mode, the output of the
line buffer is routed back to the input
of the line buffer allowing the line
buffer contents to be read multiple
times.
Bit 1 of Configuration Register 3
allows the line buffers to be loaded in
parallel. When Bit 1 is “1”, the input
register (DIN
11-0
) loads all seven line
buffers in parallel. This allows all the
line buffers to be preloaded with data
in the amount of time it normally
takes to load a single line buffer.
VSHEN enables or disables the
loading of data into the line buffers
when the device is in Dimensionally
Separate Mode (see the VSHEN
section for a full discussion). When in
Orthogonal Mode, VSHEN also
enables or disables the loading of data
into the input register (DIN
11-0
) and
the forward and reverse I/ D Registers.
It is important to note that in Or-
thogonal Mode, either HSHEN or
VSHEN can disable the loading of
data into the input register (DIN
11-0
),
I/ D Registers, and line buffers. Both
must be active to enable data loading
in Orthogonal Mode.
Interleaved Data
The vertical filter is capable of
handling interleaved data. The
number of data sets it can handle is
determined by the number of data
values contained in a video line. If
the interleaved video line has 3076
data values or less, the vertical filter
can handle it no matter how many
data sets are interleaved together.
BITS
FUNCTION
DESCRIPTION
11-0
Line Buffer Length
See Line Buffer Description Section
T
ABLE
4.
C
ONFIGURATION
R
EGISTER
2 – A
DDRESS
202H
BITS
FUNCTION
DESCRIPTION
0
Line Buffer Mode
0 : Delay Mode
1 : Recirculate Mode
1
Line Buffer Load
0 : Normal Load
1 : Parallel Load
11-2
Reserved
Must be set to “0”
T
ABLE
5.
C
ONFIGURATION
R
EGISTER
3 – A
DDRESS
203H
BITS
FUNCTION
DESCRIPTION
0
HV Filter Mode
0 : Orthogonal Mode
1 : Dimensionally Separate
1
HV Direction
0 : Horizontal to Vertical
1 : Vertical to Horizontal
3-2
Orthogonal Kernel Size
00: 3-3 Kernel
01: 5-5 Kernel
10: 7-7 Kernel
11: Not Used
4
Limit Register Load Control
0 : Limit Registers Always Enabled
1 : Limit Registers Under Shift Enable Control
11-5
Reserved
Must be set to “0”
T
ABLE
6.
C
ONFIGURATION
R
EGISTER
4 – A
DDRESS
204H
BITS
FUNCTION
DESCRIPTION
0
Vertical Limit Enable
0 : Vertical Limiting Disabled
1 : Vertical Limiting Enabled
1
Horizontal Limit Enable
0 : Horizontal Limiting Disabled
1 : Horizontal Limiting Enabled
11-2
Reserved
Must be set to “0”
T
ABLE
7.
C
ONFIGURATION
R
EGISTER
5 – A
DDRESS
205H
相关PDF资料 |
PDF描述 |
|---|---|
| LF3310 | Horizontal / Vertical Digital Image Filter |
| LF3310QC15 | Horizontal / Vertical Digital Image Filter |
| LF3330QC12 | Vertical Digital Image Filter |
| LF3330QC15 | Vertical Digital Image Filter |
| LF43168 | Dual 8-Tap FIR Filter |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LF3310QC15 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:Horizontal / Vertical Digital Image Filter |
| LF3310QC18 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Digital Filter |
| LF3310QC25 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Digital Filter |
| LF3311 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:Horizontal / Vertical Digital Image Filter |
| LF3312 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:12-Mbit Frame Buffer / FIFO |
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