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参数资料
| 型号： | LF3310QC12 |
| 厂商： | LOGIC DEVICES INC |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | Horizontal / Vertical Digital Image Filter |
| 中文描述： | 12-BIT, DSP-DIGITAL FILTER, PQFP144 |
| 封装： | PLASTIC, QFP-144 |
| 文件页数： | 4/21页 |
| 文件大小： | 287K |
| 代理商： | LF3310QC12 |
DEVICES INCORPORATED
LF3310
Horizontal / Vertical Digital Image Filter
4
Video Imaging Products
11/08/2001-LDS.3310-H
HCEN —Horizontal Coefficient
Address Enable
When HCEN is LOW, data on HCA
7-0
is latched into the Horizontal Coeffi-
cient Address Register on the rising
edge of CLK. When HCEN is HIGH,
data on HCA
7-0
is not latched and the
register’s contents will not be
changed.
VLD — Vertical Coefficient Load
When VLD is LOW, data on VCF
11-0
is latched into the Vertical LF
Interface
TM
on the rising edge of CLK.
When VLD is HIGH, data can not be
latched into the Vertical LF
Interface
TM
. When enabling the LF
Interface
TM
for data input, a HIGH to
LOW transition of VLD is required in
order for the input circuitry to func-
tion properly. Therefore, VLD must
be set HIGH immediately after power
up to ensure proper operation of the
input circuitry (see the LF Interface
TM
section for a full discussion).
VCEN — Vertical Coefficient Address
Enable
When VCEN is LOW, data on VCA
7-0
is latched into the Vertical Coefficient
Address Register on the rising edge of
CLK. When VCEN is HIGH, data on
VCA
7-0
is not latched and the
register’s contents will not be
changed.
TXFR — Horizontal Filter LIFO
Transfer Control
TXFR is used to change which LIFO in
the data reversal circuitry sends data to
the reverse data path and which LIFO
receives data from the forward data
path. When TXFR goes LOW, the LIFO
sending data to the reverse data path
becomes the LIFO receiving data from
the forward data path, and the LIFO
receiving data from the forward data
path becomes the LIFO sending data to
the reverse data path. The device must
see a HIGH to LOW transition of TXFR
in order to switch LIFOs.
HACC —Horizontal Accumulator
Control
When HACC is HIGH, the horizontal
accumulator is enabled for accumula-
tion and the accumulator output
register is disabled for loading. When
HACC is LOW, no accumulation is
performed and the accumulator
output register is enabled for loading.
HACC is latched on the rising edge of
CLK.
VACC — Vertical Accumulator Control
When VACC is HIGH, the vertical
accumulator is enabled for accumula-
tion and the accumulator output
register is disabled for loading. When
VACC is LOW, no accumulation is
performed and the accumulator
output register is enabled for loading.
VACC is latched on the rising edge of
CLK.
HSHEN — Horizontal Shift Enable
HSHEN enables or disables the
loading of data into the forward and
reverse I/ D Registers in the horizon-
tal filter when the device is in Dimen-
sionally Separate Mode. If the device
is configured such that the horizontal
filter feeds the vertical filter, HSHEN
also enables or disables the loading of
data into the input register (DIN
11-0
).
If the device is configured such that
the vertical filter feeds the horizontal
filter and the vertical limit register is
under shift control, HSHEN also
enables or disables the loading of data
into the vertical limit register in the
vertical Round/ Select/ Limit circuitry.
In Orthogonal Mode, HSHEN also
enables or disables the loading of data
into the input register (DIN
11-0
) and
the line buffers in the vertical filter. It
is important to note that in Orthogo-
nal Mode, either HSHEN or VSHEN
can disable data loading. Both must
be active to enable data loading in
Orthogonal Mode. Also in Orthogo-
nal Mode, the horizontal and vertical
limit registers can not be disabled.
When HSHEN is LOW, data is loaded
into and shifted through the registers
HSHEN controls and the forward and
reverse I/ D Registers on the rising
edge of CLK. When HSHEN is
HIGH, data is not loaded into or
shifted through the registers HSHEN
controls and the I/ D Registers, and
their contents will not be changed.
HSHEN is latched on the rising edge
of CLK.
VSHEN — Vertical Shift Enable
VSHEN enables or disables the
loading of data into the line buffers in
the vertical filter when the device is in
Dimensionally Separate Mode. If the
device is configured such that the
vertical filter feeds the horizontal
filter, VSHEN also enables or disables
the loading of data into the input
register (DIN
11-0
). If the device is
configured such that the horizontal
filter feeds the vertical filter and the
horizontal limit register is under shift
control, VSHEN also enables or
disables the loading of data into the
horizontal limit register in the hori-
zontal Round/ Select/ Limit circuitry.
In Orthogonal Mode, VSHEN also
enables or disables the loading of data
into the input register (DIN
11-0
) and
the forward and reverse I/ D Registers
in the horizontal filter. It is important
to note that in Orthogonal Mode,
either HSHEN or VSHEN can disable
data loading. Both must be active to
enable data loading in Orthogonal
Mode. Also in Orthogonal Mode, the
horizontal and vertical limit registers
can not be disabled.
When VSHEN is LOW, data is loaded
into and shifted through the registers
VSHEN controls and the line buffers
on the rising edge of CLK. When
VSHEN is HIGH, data is not loaded
into or shifted through the registers
VSHEN controls and the line buffers,
and their contents will not be
changed. VSHEN is latched on the
rising edge of CLK.
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| LF3310QC15 | Horizontal / Vertical Digital Image Filter |
| LF3330QC12 | Vertical Digital Image Filter |
| LF3330QC15 | Vertical Digital Image Filter |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LF3310QC15 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:Horizontal / Vertical Digital Image Filter |
| LF3310QC18 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Digital Filter |
| LF3310QC25 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Digital Filter |
| LF3311 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:Horizontal / Vertical Digital Image Filter |
| LF3312 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:12-Mbit Frame Buffer / FIFO |
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