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参数资料
| 型号： | LF3310QC12 |
| 厂商： | LOGIC DEVICES INC |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | Horizontal / Vertical Digital Image Filter |
| 中文描述： | 12-BIT, DSP-DIGITAL FILTER, PQFP144 |
| 封装： | PLASTIC, QFP-144 |
| 文件页数： | 11/21页 |
| 文件大小： | 287K |
| 代理商： | LF3310QC12 |
DEVICES INCORPORATED
Video Imaging Products
11
LF3310
Horizontal / Vertical Digital Image Filter
11/08/2001-LDS.3310-H
Vertical Rounding
The vertical filter output may be
rounded by adding the contents of
one of the sixteen vertical round
registers to the vertical filter output
(see Figure 11). Each round register is
32-bits wide and user-programmable.
This allows the filter’s output to be
rounded to any precision required.
Since any 32-bit value may be
programmed into the round registers,
the device can support complex
rounding algorithms as well as
standard Half-LSB rounding.
VRSL
3-0
determines which of the
sixteen vertical round registers are
used in the rounding operation. A
value of 0 on VRSL
3-0
selects vertical
round register 0. A value of 1 selects
vertical round register 1 and so on.
VRSL
3-0
may be changed every clock
cycle if desired. This allows the
rounding algorithm to be changed
every clock cycle. This is useful when
filtering interleaved data. If rounding
is not desired, a round register should
be loaded with 0 and selected as the
register used for rounding. Round
register loading is discussed in the LF
Interface
TM
section.
Vertical Select
The word width of the vertical filter
output is 32-bits. However, only
12-bits may be sent to the filter
output. The vertical filter select
circuitry determines which 12-bits are
passed (see Table 1). The vertical
select registers control the vertical
select circuitry. There are sixteen
vertical select registers. Each select
REGISTER
ADDRESS (HEX)
0
1
800
801
14
15
80E
80F
T
ABLE
9. H
RZ
. R
OUND
R
EGISTERS
REGISTER
ADDRESS (HEX)
0
1
C00
C01
14
15
C0E
C0F
T
ABLE
11. H
RZ
. L
IMIT
R
EGISTERS
REGISTER
ADDRESS (HEX)
0
1
A00
A01
14
15
A0E
A0F
T
ABLE
12. V
RT
. R
OUND
R
EGISTERS
REGISTER
ADDRESS (HEX)
0
1
E00
E01
14
15
E0E
E0F
T
ABLE
14. V
RT
. L
IMIT
R
EGISTERS
register is 5-bits wide and
user-programmable. VRSL
3-0
deter-
mines which of the sixteen vertical
select registers are used in the vertical
select circuitry. A value of 0 on
VRSL
3-0
selects vertical select register
0. A value of 1 selects vertical select
register 1 and so on. VRSL
3-0
may be
changed every clock cycle if desired.
This allows the 12-bit window to be
changed every clock cycle. This is
useful when filtering interleaved
data. Select register loading is
discussed in the LF Interface
TM
section.
Vertical Limiting
An output limiting function is pro-
vided for the output of the vertical
filter. The vertical limit registers
determine the valid range of output
values when limiting is enabled (Bit 0
in Configuration Register 5). There
11 10 9
DESCRIPTION
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Coefficient Banks
Configuration Registers
Horizontal Select Registers
Vertical Select Registers
Horizontal Round Registers
Vertical Round Registers
Horizontal Limit Registers
Vertical Limit Registers
T
ABLE
8. HCF/VCF
11-9
D
ECODE
are sixteen 24-bit vertical limit
registers. VRSL
3-0
determines which
vertical limit register is used during
the limit operation. A value of 0 on
VRSL
3-0
selects vertical limit register
0. A value of 1 selects vertical limit
register 1 and so on. Each limit
register contains both an upper and
lower limit value. If the value fed to
the limiting circuitry is less than the
lower limit, the lower limit value is
passed as the filter output. If the
value fed to the limiting circuitry is
greater than the upper limit, the upper
limit value is passed as the filter output.
VRSL
3-0
may be changed every clock
cycle if desired. This allows the limit
range to be changed every clock cycle.
This is useful when filtering interleaved
data. When loading limit values into
the device, the upper limit must be
greater than the lower limit. Limit
register loading is discussed in the LF
Interface
TM
section.
REGISTER
ADDRESS (HEX)
0
1
400
401
14
15
40E
40F
T
ABLE
10. H
RZ
. S
ELECT
R
EGISTERS
REGISTER
ADDRESS (HEX)
0
1
600
601
14
15
60E
60F
T
ABLE
13. V
RT
. S
ELECT
R
EGISTERS
相关PDF资料 |
PDF描述 |
|---|---|
| LF3310 | Horizontal / Vertical Digital Image Filter |
| LF3310QC15 | Horizontal / Vertical Digital Image Filter |
| LF3330QC12 | Vertical Digital Image Filter |
| LF3330QC15 | Vertical Digital Image Filter |
| LF43168 | Dual 8-Tap FIR Filter |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LF3310QC15 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:Horizontal / Vertical Digital Image Filter |
| LF3310QC18 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Digital Filter |
| LF3310QC25 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Digital Filter |
| LF3311 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:Horizontal / Vertical Digital Image Filter |
| LF3312 | 制造商:LOGIC 制造商全称:LOGIC 功能描述:12-Mbit Frame Buffer / FIFO |
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