3-22
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
HSTL15_II
HSTL_15 class II
0.10
0.12
0.14
ns
HSTL15_III
HSTL_15 class III
0.10
0.12
0.14
ns
HSTL15D_I
Differential HSTL 15 class I
0.08
0.10
0.11
ns
HSTL15D_III
Differential HSTL 15 class III
0.10
0.12
0.14
ns
SSTL33_I
SSTL_3 class I
-0.05
-0.06
-0.07
ns
SSTL33_II
SSTL_3 class II
0.40
0.48
0.56
ns
SSTL33D_I
Differential SSTL_3 class I
-0.05
-0.06
-0.07
ns
SSTL33D_II
Differential SSTL_3 class II
0.40
0.48
0.56
ns
SSTL25_I
SSTL_2 class I
0.05
0.07
0.08
ns
SSTL25_II
SSTL_2 class II
0.25
0.30
0.35
ns
SSTL25D_I
Differential SSTL_2 class I
0.05
0.07
0.08
ns
SSTL25D_II
Differential SSTL_2 class II
0.25
0.30
0.35
ns
SSTL18_I
SSTL_1.8 class I
0.01
ns
SSTL18D_I
Differential SSTL_1.8 class I
0.01
ns
LVTTL33_4mA
LVTTL 4mA drive
0.09
0.11
0.13
ns
LVTTL33_8mA
LVTTL 8mA drive
0.07
0.08
0.09
ns
LVTTL33_12mA
LVTTL 12mA drive
-0.03
-0.04
-0.05
ns
LVTTL33_16mA
LVTTL 16mA drive
0.36
0.43
0.51
ns
LVTTL33_20mA
LVTTL 20mA drive
0.28
0.33
0.39
ns
LVCMOS33_4mA
LVCMOS 3.3 4mA drive
0.09
0.11
0.13
ns
LVCMOS33_8mA
LVCMOS 3.3 8mA drive
0.07
0.08
0.09
ns
LVCMOS33_12mA
LVCMOS 3.3 12mA drive
-0.03
-0.04
-0.05
ns
LVCMOS33_16mA
LVCMOS 3.3 16mA drive
0.36
0.43
0.51
ns
LVCMOS33_20mA
LVCMOS 3.3 20mA drive
0.28
0.33
0.39
ns
LVCMOS25_4mA
LVCMOS 2.5 4mA drive
0.18
0.21
0.25
ns
LVCMOS25_8mA
LVCMOS 2.5 8mA drive
0.10
0.12
0.14
ns
LVCMOS25_12mA
LVCMOS 2.5 12mA drive
0.00
ns
LVCMOS25_16mA
LVCMOS 2.5 16mA drive
0.22
0.26
0.31
ns
LVCMOS25_20mA
LVCMOS 2.5 20mA drive
0.14
0.16
0.19
ns
LVCMOS18_4mA
LVCMOS 1.8 4mA drive
0.15
0.18
0.21
ns
LVCMOS18_8mA
LVCMOS 1.8 8mA drive
0.06
0.08
0.09
ns
LVCMOS18_12mA
LVCMOS 1.8 12mA drive
0.01
ns
LVCMOS18_16mA
LVCMOS 1.8 16mA drive
0.16
0.19
0.22
ns
LVCMOS15_4mA
LVCMOS 1.5 4mA drive
0.26
0.31
0.36
ns
LVCMOS15_8mA
LVCMOS 1.5 8mA drive
0.04
0.05
ns
LVCMOS12_2mA
LVCMOS 1.2 2mA drive
0.36
0.43
0.50
ns
LVCMOS12_6mA
LVCMOS 1.2 6mA drive
0.08
0.10
0.11
ns
LVCMOS12_4mA
LVCMOS 1.2 4mA drive
0.36
0.43
0.50
ns
PCI33
1.05
1.26
1.46
ns
1. Timing adders are characterized but not tested on every device.
2. LVCMOS timing measured with the load specified in Switching Test Conditions table of this document.
3. All other standards according to the appropriate specification.
Timing v.G 0.30
LatticeECP/EC Family Timing Adders1, 2, 3 (Continued)
Over Recommended Operating Conditions
Buffer Type
Description
-5
-4
-3
Units