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参数资料
型号： LFEC10E-5QN208C
厂商： Lattice Semiconductor Corporation
文件页数： 90/163页
文件大小： 0K
描述： IC FPGA 10.2KLUTS 147I/O 208QFP
标准包装： 24
系列： EC
逻辑元件/单元数： 10200
RAM 位总计： 282624
输入/输出数： 147
电源电压： 1.14 V ~ 1.26 V
安装类型： 表面贴装
工作温度： 0°C ~ 85°C
封装/外壳： 208-BFQFP
供应商设备封装： 208-PQFP（28x28）
2-29
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-34. LatticeECP/EC Banks
LatticeECP/EC devices contain two types of sysI/O buffer pairs.
1.
Top and Bottom sysI/O Buffer Pairs (Single-Ended Outputs Only)
The sysI/O buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers
and two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also
be configured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
Only the I/Os on the top and bottom banks have programmable PCI clamps. These I/O banks also support hot
socketing with IDK less than 1mA. Note that the PCI clamp is enabled after VCC, VCCAUX and VCCIO are at valid
operating levels and the device has been configured.
2.
Left and Right sysI/O Buffer Pairs (Differential and Single-Ended Outputs)
The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two
sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. The refer-
enced input buffer can also be configured as a differential input. In these banks the two pads in the pair are
described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O,
and the comp (complementary) pad is associated with the negative side of the differential I/O.
Only the left and right banks have LVDS differential output drivers. See the IDK specification for I/O leakage cur-
rent during power-up.
V
REF1(2)
GND
Bank
2
V
CCIO2
V
REF2(2)
V
REF1(3)
GND
Bank
3
V
CCIO3
V
REF2(3)
V
REF1(7)
GND
TOP
LEFT
RIGHT
BOTTOM
Bank
7
V
CCIO7
V
REF2(7)
V
REF1(6)
GND
Bank
6
V
CCIO6
V
REF2(6)
V
REF1(5)
GND
Bank 5
V
CCIO5
V
REF2(5)
V
REF1(4)
GND
Bank 4
V
CCIO4
V
REF2(4)
V
REF1(0)
GND
Bank 0
V
CCIO0
V
REF2(0)
V
REF1(1)
GND
Bank 1
V
CCIO1
V
REF2(1)
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