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| 型号： | LH28F320SKTD-ZR |
| 厂商： | Sharp Microelectronics |
| 文件页数： | 26/70页 |
| 文件大小： | 0K |
| 描述： | IC FLASH 32MBIT 70NS 48TSOP |
| 产品变化通告： | Symmetrical Flash Discontinuation 01/Dec/2005 |
| 标准包装： | 50 |
| 格式 - 存储器： | 闪存 |
| 存储器类型： | FLASH |
| 存储容量： | 32M（4M x 8，2M x 16） |
| 速度： | 70ns |
| 接口： | 并联 |
| 电源电压： | 2.7 V ~ 3.6 V，4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 48-TSOP |
| 供应商设备封装： | 48-TSOP |
| 包装： | 托盘 |
| 其它名称： | 425-2463 LHF32KZR |
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LHF32KZR
Table 14. Status Register Definition
23
WSMS
7
BESS
6
ECBLBS
5
WSBLBS
4
VPPS
3
WSS
2
DPS
1
R
0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
SR.6 = BLOCK ERASE SUSPEND STATUS
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS
STATUS
1 = Error in Erase or Clear Blocl Lock-Bits
0 = Successful Erase or Clear Block Lock-Bits
SR.4 = WRITE AND SET BLOCK LOCK-BIT STATUS
1 = Error in Write or Set Block Lock-Bit
0 = Successful Write or Set Block Lock-Bit
SR.3 = V PP STATUS
1 = V PP Low Detect, Operation Abort
0 = V PP OK
SR.2 = WRITE SUSPEND STATUS
1 = Write Suspended
0 = Write in Progress/Completed
SR.1 = DEVICE PROTECT STATUS
1 = Block Lock-Bit and/or WP# Lock Detected,
Operation Abort
0 = Unlock
Check STS or SR.7 to determine block erase, bank
erase, (multi) word/byte write or block lock-bit
configuration completion.
SR.6-0 are invalid while SR.7="0".
If both SR.5 and SR.4 are "1"s after a block erase, bank
erase, (multi) word/byte write, block lock-bit
configuration or STS configuration attempt, an improper
command sequence was entered.
SR.3 does not provide a continuous indication of V PP
level. The WSM interrogates and indicates the V PP level
only after block erase, bank erase, (multi) word/byte
write or block lock-bit configuration command
sequences. SR.3 is not guaranteed to reports accurate
feedback only when V PP ≠ V PPH1/2/3 .
SR.1 does not provide a continuous indication of block
lock-bit values. The WSM interrogates block lock-bit,
and WP# only after block erase, bank erase, (multi)
word/byte write or block lock-bit configuration command
sequences. It informs the system, depending on the
attempted operation, if the block lock-bit is set and/or
WP# is not V IH . Reading the block lock configuration
codes after writing the Read Identifier Codes command
indicates block lock-bit status.
SR.0 is reserved for future use and should be masked
out when polling the status register.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
Table 14.1. Extended Status Register Definition
SMS
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
NOTES:
XSR.7 = STATE MACHINE STATUS
1 = Multi Word/Byte Write available
0 = Multi Word/Byte Write not available
After issue a Multi Word/Byte Write command: XSR.7
indicates that a next Multi Word/Byte Write command is
available.
XSR.6-0=RESERVED FOR FUTURE ENHANCEMENTS
XSR.6-0 is reserved for future use and should be
masked out when polling the extended status register.
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