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参数资料
| 型号： | LM12438CIWMX |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封装： | SOP-28 |
| 文件页数： | 28/80页 |
| 文件大小： | 1552K |
| 代理商： | LM12438CIWMX |
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60 Operational Information (Continued)
Bits 12 – 15
store the user-programmable acquisition time
The Sequencer keeps the internal SH in the acquisition
mode for a fixed number of clock cycles (nine clock cycles
for 12-bit a sign conversions and two clock cycles for 8-bit
a
sign conversions or ‘‘watchdog’’ comparisons) plus a
variable number of clock cycles equal to twice the value
stored in Bits 12 – 15 Thus the SH’s acquisition time is (9
a
2D) clock cycles for 12-bit a sign conversions and (2 a
2D) clock cycles for 8-bit a sign conversions or ‘‘watch-
dog’’ comparisons where D is the value stored in Bits 12 –
15 The minimum acquisition time compensates for the typi-
cal internal multiplexer series resistance of 2 kX and any
additional delay created by Bits 12 – 15 compensates for
source resistances greater than 60X 80X
The necessary
acquisition time is determined by the source impedance at
the multiplexer input If the source resistance RS k 60X
and the clock frequency is 8 MHz the value stored in bits
12 – 15 (D) can be 0000 If RS l 60X the following equa-
tions determine the value that should be stored in
bits 12 – 15
D e 045 x RS xfCLK
for 12-bits a sign
D e 036 x RS xfCLK
for 8-bits a sign and ‘‘watchdog’’
RS is in kX and fCLK is in MHz Round the result to the next
higher integer value If the value of 0 obtained from the
expressions above is greater than 15 it is advisable to lower
the source impedance by using an analog buffer between
the signal source and the LM12 L 438’s multiplexer inputs
The value of D can also be used to compensate for the
settling or response time of external processing circuits con-
nected between the LM12434’s MUXOUT and SH IN pins
Instruction RAM Bank 2 RP e 01
The second Instruction RAM section is selected by placing
‘‘01’’ in Bits 8 and 9 of the Configuration register
Bits 0 – 7
hold ‘‘watchdog’’ limit
1
When Bit 11 of Instruc-
tion RAM ‘‘00’’ is set to a ‘‘1’’
the LM12434 and
LM12 L 438 performs a ‘‘watchdog’’ comparison of the
sampled analog input signal with the limit
1 value first
followed by a comparison of the same sampled analog input
signal with the value found in limit
2 (Instruction RAM
‘‘10’’)
Bit 8
holds limit
1’s sign
Bit 9
’s state determines the limit condition that generates a
‘‘watchdog’’ interrupt A ‘‘1’’ causes a voltage greater than
limit
1 to generate an interrupt while a ‘‘0’’ causes a volt-
age less than limit
1 to generate an interrupt
Bits 10 – 15
are not used
Instruction RAM Bank 3 RP e 10
The third Instruction RAM section is selected by placing
‘‘10’’ in Bits 8 and 9 of the Configuration register
Bits 0 – 7
hold ‘‘watchdog’’ limit
2
When Bit 11 of Instruc-
tion RAM ‘‘00’’ is set to a ‘‘1’’
the LM12434 and
LM12 L 438 performs a ‘‘watchdog’’ comparison of the
sampled analog input signal with the limit
1 value first (In-
struction RAM ‘‘01’’) followed by a comparison of the same
sampled analog input signal with the value found in limit
2
Bit 8
holds limit
2’s sign
Bit 9
’s state determines the limit condition that generates a
‘‘watchdog’’ interrupt A ‘‘1’’ causes a voltage greater than
limit
2 to generate an interrupt while a ‘‘0’’ causes a volt-
age less than limit
2 to generate an interrupt
Bits 10 – 15
are not used
TABLE III LM12 L 438 Operating Mode Input Channel Selection through Input Multiplexer
Normal Operating Mode
Non-Inverting Input
Input Channel to Be
Inverting Input
Input Channel to Be
Channel Selection Bits
Connected to AD
Channel Selection Bits
Connected to AD
in Instruction Register
Non-Inverting Input
in Instruction Register
Inverting Input
D4 D3 D2
(INa)
D7 D6 D5
(INb)
000
IN0
000
GND
001
IN1
001
IN1
010
IN2
010
IN2
011
IN3
011
IN3
100
IN4
100
IN4
101
IN5
101
IN5
110
IN6
110
IN6
111
IN7
111
IN7
34
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