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| 型号： | LM12438CIWMX |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封装： | SOP-28 |
| 文件页数： | 32/80页 |
| 文件大小： | 1552K |
| 代理商： | LM12438CIWMX |
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60 Operational Information (Continued)
Bit 6
no interrupt is associated with this bit Don’t care con-
dition
Bit 7
is set to ‘‘1’’ when the DAS returns from standby to
active mode (see Note 22)
Bits 8 – 10
hold the Sequencer’s current instruction number
while it is running
Bits 11 – 15
hold the current number of conversion results
stored in FIFO but have not been read by the user After
each conversion the result will be stored in the FIFO and
the contents of these bits incremented by one Each single
read from FIFO decrements the contents of these bits by
one If more than 32 conversion results being stored in FIFO
the numbers on these bits roll over from ‘‘11111’’ to
‘‘00000’’ and continue incrementing If reads are performed
from FIFO more than the number of conversions stored in it
the contents of these bits roll back from ‘‘00000’’ to
‘‘11111’’ and continue decrementing
626 Limit Status Register
This read-only register is located at address 1101 This reg-
ister is used in tandem with the Limit
1 and Limit
2 regis-
ters in the Instruction RAM Whenever a given instruction’s
input voltage exceeds the limit set in its corresponding Limit
register ( 1or
2) a bit corresponding to the instruction
number is set in the Limit Status register Any of the active
(‘‘1’’) Limit Status flags are reset to ‘‘0’’ whenever this regis-
ter is read or a device reset is issued (see Bit 1 in the Con-
figuration register) This register holds the status of limits
1 and
2 for each of the eight instructions
Bits 0 – 7
show the Limit
1 status Each bit will be set high
(‘‘1’’) when the corresponding instruction’s input voltage ex-
ceeds the threshold stored in the instruction’s Limit
1 reg-
ister When for example instruction 3 is a ‘‘watchdog’’ op-
eration (Bit 11 is set high) and the input for instruction 3
meets the magnitude andor polarity data stored in instruc-
tion 3’s Limit
1 register Bit 3 in the Limit Status register
will be set to a ‘‘1’’
Bits 8 – 15
show the Limit
2 status Each bit will be set
high (‘‘1’’) when the corresponding instruction’s input volt-
age exceeds the threshold stored in the instruction’s Limit
2 register When for example the input to instruction 6
meets the value stored in instruction 6’s Limit
2 register
Bit 14 in the Limit Status register will be set to a ‘‘1’’
627 Timer
The LM12434 and LM12 L 438 have an on-board 16-bit
timer that includes a 5-bit pre-scaler It uses the clock signal
applied to pin 23 as its input It can generate time intervals
of 0 through 221 clock cycles in steps of 25 This time inter-
val can be used to delay the execution of instructions It can
also be used to slow the conversion rate when converting
slowly changing signals This can reduce the amount of re-
dundant data stored in the FIFO and retrieved by the con-
troller
The user-defined timing value used by the Timer is stored in
the 16-bit READWRITE Timer register at location 1011 and
is pre-loaded automatically Bits 0 – 7 hold the preset value’s
low byte and Bits 8 – 15 hold the high byte The Timer is
activated by the Sequencer only if the current instruction’s
Bit 9 is set (‘‘1’’) If the equivalent decimal value ‘‘N’’
(0 s N s 216 b 1) is written inside the 16-bit Timer register
and the Timer is enabled by setting an instruction’s bit 9 to a
‘‘1’’ the Sequencer will delay that instruction’s execution by
halting at state 3 (S3) as shown in
Figure 11 for 32 c N a
2 clock cycles
628 FIFO
The result of each conversion is stored in an internal read-
only FIFO (First-In First-Out) register It is located at ad-
dress 1100 This register has 32 16-bit wide locations Each
location holds 13 bits of conversion data Bits 0 – 3 hold the
four LSBs in the 12 bits a sign mode or ‘‘1110’’ in the 8 bits
a
sign mode Bits 4 – 11 hold the eight MSBs and Bit 12
holds the sign bit Bits 13 – 15 can hold either the sign bit
extending the register’s two’s complement data format to a
full sixteen bits or the instruction address that generated the
conversion and the resulting data These modes are select-
ed according to the logic state of the Configuration regis-
ter’s Bit 5
The FIFO status should be read in the Interrupt Status regis-
ter (Bits 11 – 15) to determine the number of conversion re-
sults that are held in the FIFO before retrieving them This
will help prevent conversion data corruption that may take
place if the number of reads are greater than the number of
conversion results contained in the FIFO Trying to read the
FIFO when it is empty may corrupt new data being written
into the FIFO Writing more than 32 conversion results into
the FIFO by the ADC results in loss of the first conversion
results Therefore to prevent data loss it is recommended
that the LM12434 and LM12 L 438’s interrupt capability be
used to inform the system controller that the FIFO is full
Bits 0 – 12
hold 12-bit a sign conversion data Bits 0 – 3 will
be 1110 when using 8-bit plus sign resolution
Bits 13 – 15
hold either the instruction responsible for the
associated conversion data or the sign bit Either mode is
selected with Bit 5 in the Configuration register
Using the FIFO’s full depth is achieved as follows Set the
value of the Interrupt Enable registers’s Bits 11 – 15 to
00000 and the Interrupt Enable register’s Bit 2 to a ‘‘1’’ This
generates an external interrupt when the 31st conversion is
stored in the FIFO This gives the host processor a chance
to send a ‘‘0’’ to the LM12434 and LM12 L 438’s Start bit
(Configuration register) and halt the ADC before it com-
pletes the 32nd conversion The Sequencer halts after the
current (32) conversion is completed The conversion data
is then transferred to the FIFO and occupies the 32nd loca-
tion FIFO overflow is avoided if the Sequencer is halted
before the start of the 32nd conversion by placing a ‘‘0’’ in
the Start bit (Configuration register) It is important to re-
member that the Sequencer continues to operate even if
a FIFO interrupt (INT 2) is internally or externally gener-
ated
The only mechanisms that stop the Sequencer are an
instruction with the PAUSE bit set to ‘‘1’’ (halts before in-
struction execution) placing a ‘‘0’’ in the Configuration reg-
ister’s START bit or placing a ‘‘1’’ in the Configuration reg-
ister’s RESET bit
38
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