参数资料
型号: LM1971N/NOPB
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PDIP8
封装: 0.300 INCH, PLASTIC, DIP-8
文件页数: 10/11页
文件大小: 293K
代理商: LM1971N/NOPB
Application Information (Continued)
ATTENUATION STEP SCHEME
The fundamental attenuation step scheme for the LM1971 is
shown in Figure 5. It is also possible to obtain any integer
value attenuation step through programming, in addition to
the 2 dB and 4 dB steps shown in Figure 5. All higher
attenuation step schemes can have clickless and popless
performance. Although it is possible to “skip” attenuation
points by not sending all of the data, clickless and popless
performance will suffer. It is highly recommended that all of
the data points should be sent for each attenuation level.
This ensures flawless operation and performance when
making steps larger than 1 dB.
INPUT IMPEDANCE
The input impedance of a Pot is constant at a nominal
40 k
. Since the LM1971 is a single-supply operating de-
vice, it is necessary to have both input and output coupling
caps as shown in Figure 1. To ensure full low-frequency
response,a1F coupling cap should be used.
OUTPUT IMPEDANCE
The output impedance of a Pot varies typically between
25 k
and 35 k and changes nonlinearly with step
changes. Since a Pot is made up of a resistor ladder
network with logarithmic attenuation, the output impedance
is nonlinear. Due to this configuration, a Pot cannot be
considered as a linear potentiometer; it is a logarithmic
attenuator.
The linearity of a Pot cannot be measured directly without a
buffer because the input impedance of most measurement
systems is not high enough to provide the required accuracy.
The lower impedance of the measurement system would
load down the output and an incorrect reading would result.
To prevent loading, a JFET input op amp should be used as
the buffer/amplifier.
OUTPUT BUFFERING
There are two performance issues to be aware of that are
related to a Pot’s output stage. The first concern is to
prevent audible clicks with attenuation changes, while the
second is to prevent loading and subsequent linearity errors.
The output stage of a Pot needs to be buffered with a low
input bias current op amp to keep DC shifts inaudible. Addi-
tionally, the output of Pot needs to see a high impedance to
keep linearity errors low.
Attenuation level changes cause changes in the output im-
pedance of a Pot. Output impedance changes in the pres-
ence of a large input bias current for a buffer/amplifier will
cause a DC shift to occur. Neglecting amplifier gains and
speaker sensitivities, the audibility of a DC shift is dependent
upon the output impedance change times the required input
bias current. As an example, a 5 k
impedance change
timesa1A bias current results ina5mVDC shift; a level
that is barely audible without any music material in the
system. An op amp with a bias current of 200 pA for the
same 5 k
change results in an inaudible 1 V DC shift.
Since the worst case output impedance changes are on the
order of several k
, a bias current much less than 1 A is
required for highest performance. In order to further quantify
DC shifts, please refer to the Output Impedance vs Attenu-
ation graph in the Typical Performance Characteristics
section and relate worst case impedance changes to the
selected buffer/amplifier input bias current.
Without the use of a high input impedance (> 1M
)opamp
for the buffer/amplifier, loading will occur that causes linearity
errors in the signal. To ensure the highest level of perfor-
mance, a JFET or CMOS input high input impedance op
amp is required.
One common application that requires gain at the output of a
Pot is input signal volume control. Depending upon the
input source material, the LM1971 provides a means of
controlling the input signal level. With a supply voltage range
of 4.5V to 12V, the LM1971 has the ability of controlling fairly
inconsistent input source signal levels. Using an op amp with
gain at the Pot’s output, as shown in Figure 7, will also
allow the system dynamic range to be increased. JFET op
amps like the LF351 and the LF411 are well suited for this
application. If active half-supply buffering is also desired,
dual op amps like the LF353 and the LF412 could be used.
For low voltage supply applications, op amps like the CMOS
LMC6041 are preferred. This part has a supply operating
range from 4.5V–15.5V and also comes in a surface mount
package.
POT HALF-SUPPLY REFERENCING
The LM1971 operates off of a single supply, with half-supply
biasing supplied at the V
REFIN terminal (Pin 1). The easiest
and most cost effective method of providing this half-supply
is a simple resistor divider and bypass capacitor network
shown in Figure 1. The capacitor not only stabilizes the
half-supply node by “holding” the voltage nearly constant,
but also decouples high frequency signals on the supply to
ground. Signal feedthrough, power supply ripple and fluctua-
tions that are not properly filtered could cause the perfor-
mance of the LM1971 to be degraded.
A more stable half-supply node can be obtained by actively
buffering the resistor divider network with a voltage follower
as shown in Figure 6. Supply fluctuations are then isolated
by the high input impedance/low output impedance mis-
match associated with effective filtering. Since the LM1971 is
a single channel device, using a dual JFET input op amp is
optimum for both output buffering and half-supply biasing.
A 10 F capacitor or larger is recommended for better
half-supply stabilization. For added rejection of higher fre-
LM 1971 Channel Attenuation
vs Digital Step Value
(1 dB, 2 dB, and 4 dB Steps)
01235306
FIGURE 5. LM1971 Attenuation Step Scheme
LM1971
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