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参数资料
| 型号： | LM1971N/NOPB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP8 |
| 封装： | 0.300 INCH, PLASTIC, DIP-8 |
| 文件页数： | 9/11页 |
| 文件大小： | 293K |
| 代理商： | LM1971N/NOPB |
Application Information (Continued)
POT LADDER ARCHITECTURE
The Pot contains a chain of R1/R2 resistor dividers in a
ladder form, as shown in Figure 4. Each R1 is actually a
series of 8 resistors, with a CMOS switch that taps into the
resistor chain according to the attenuation level chosen. For
any given attenuation setting, there is only one CMOS switch
closed (no paralleling of ladders). The input impedance
therefore remains constant, while the output impedance
changes as the attenuation level changes. It is important to
note that the architecture is a series of resistor dividers, and
not a straight, tapped resistor, so the Pot is not a variable
resistor; it is a variable voltage divider.
01235303
*Note: Load and clock falling edges can be coincident, however, the clock falling edge cannot be delayed more than 20 ns from the falling edge of load. It is
preferrable that the falling edge of clock occurs before the falling edge of load.
FIGURE 2. Timing Diagram
01235304
FIGURE 3. Serial Data Format Transfer Process
01235305
FIGURE 4. Resistor Ladder Architecture
LM1971
www.national.com
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