参数资料
型号: LM1971N/NOPB
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PDIP8
封装: 0.300 INCH, PLASTIC, DIP-8
文件页数: 8/11页
文件大小: 293K
代理商: LM1971N/NOPB
Typical Performance Characteristics (Continued)
THD vs Freq by FFT
Output Impedance vs
Attenuation Level
01235320
01235321
Application Information
SERIAL DATA FORMAT
The LM1971 uses a 3-wire serial communication format that
is easily controlled by a microcontroller. The timing for the
3-wire set, comprised of DATA, CLOCK, and LOAD is shown
in Figure 2. As depicted in Figure 2, the LOAD line is to go
low at least 150 ns before the rising edge of the first clock
pulse and is to remain low throughout the transmission of the
16 data bits. The serial data is composed of an 8-bit address,
which must always be set to 0000 0000 to select the single
audio channel, and 8 bits for attenuation setting. For both
address data and attenuation setting data, the MSB is sent
first with the address data preceding the attenuation data.
Please refer to Figure 3 to confirm the serial data format
transfer process.
Table 1 shows the various Address and Data byte values for
different attenuation settings. Note that Address bytes other
than 0000 0000 are ignored.
POT SYSTEM ARCHITECTURE
The Pot’s digital interface is essentially a shift register
where serial data is shifted in, latched, and then decoded.
Once new data is shifted in, the LOAD line goes high,
latching in the new data. The data is then decoded and the
appropriate switch is activated to set the desired attenuation
level. This process is continued each and every time an
attenuation change is made. When the Pot is powered up,
it is placed into the Mute mode.
POT DIGITAL COMPATIBILITY
The Pot’s digital interface section is compatible with TTL or
CMOS logic. The shift register inputs act upon a threshold of
two diode drops above the ground level (Pin 3) or approxi-
mately 1.4V.
TABLE 1. Attenuator Register Set Description
Address Register (Byte 0)
MSB LSB
A7–A0
0000 0000
Channel 1
0000 0001
Ignored
0000 0010
Ignored
Data Register (Byte 1)
Contents
Attenuation (dB)
MSB LSB
D7–D0
0000 0000
0.0
0000 0001
1.0
0000 0010
2.0
0000 0011
3.0
:::::
::
0001 0000
16.0
0001 0001
17.0
0001 0010
18.0
0001 0011
19.0
:::::
::
0011 1101
61.0
0011 1110
62.0
0011 1111
96 (Mute)
0100 0000
96 (Mute)
:::::
::
1111 1110
96 (Mute)
1111 1111
96 (Mute)
LM1971
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相关代理商/技术参数
参数描述
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