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参数资料
| 型号： | LM5067SDX-1 |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 电源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, DSO10 |
| 封装： | LLP-10 |
| 文件页数： | 13/24页 |
| 文件大小： | 690K |
| 代理商： | LM5067SDX-1 |
PC Board Guidelines
The following guidelines should be followed when designing
the PC board for the LM5067:
Place the LM5067 close to the board’s input connector to
minimize trace inductance from the connector to the FET.
Place R
IN and CIN close to the VCC and VEE pins to keep
transients below the Absolute Maximum rating of the
LM5067. Transients of several volts can easily occur when
the load current is shut off.
The sense resistor (R
S) should be close to the LM5067,
and connected to it using the Kelvin techniques shown in
Figure 7.
The high current path from the board’s input to the load,
and the return path (via Q1), should be parallel and close
to each other wherever possible to minimize loop
inductance.
The VEE connection for the various components around
the LM5067 should be connected directly to each other,
and to the LM5067’s VEE pin, and then connected to the
system VEE at one point. Do not connect the various
components to each other through the high current VEE
track.
Provide adequate heat sinking for the series pass device
(Q1) to help reduce thermal stresses during turn-on and
turn-off.
The board’s edge connector can be designed to shut off
the LM5067 as the board is removed, before the supply
voltage is disconnected from the LM5067. In Figure 17 the
voltage at the UVLO/EN pin goes to VEE before V
SYS is
removed from the LM5067 due to the shorter edge
connector pin. When the board is inserted into the edge
connector, the system voltage is applied to the LM5067’s
VEE and VCC pins before voltage is applied to the UVLO/
EN pin.
If power dissipation within the LM5067 is high, an exposed
copper pad should be provided beneath the package, and
that pad should be connected to exposed copper on the
board’s other side with as many vias as possible. If the LLP
package is used, the exposed pad on the package bottom
should be soldered to the board’s copper pad. The
package’s exposed pad is at the VEE voltage. See the
Thermal Considerations section.
30030962
FIGURE 17. Suggested Board Connector Design
Thermal Considerations
The LM5067 should be operated so that its junction temper-
ature does not exceed 125°C. The junction temperature is
equal to:
T
J = TA + (R
θJA x PD)
where T
A is the ambient temperature, and R
θJA is the thermal
resistance of the LM5067. P
D is the power dissipated within
the LM5067, calculated from:
P
D = 13V x ICC
where I
CC is the current into the VCC pin (the current through
the R
IN resistor). The following table provides values for
RθJA and RθJC for the MSOP-10 and LLP-10 packages, 2 layer
and 4 layer PC boards, and various number of heat transfer-
ring vias beneath the IC package. It is obvious that adding just
one via to other heat dissipating layers in the PC board affects
RθJA very significantly. If the LLP-10 package is used, the ex-
posed pad on the bottom should be soldered to a copper
plane, and that plane should extend out from beneath the IC
package as well as be connected to exposed copper on the
board’s other side using as many vias as possible. The ex-
posed pad is internally connected to the IC substrate, and is
at VEE potential.
www.national.com
20
LM5067
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