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参数资料
| 型号： | LM5067SDX-1 |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 电源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, DSO10 |
| 封装： | LLP-10 |
| 文件页数： | 6/24页 |
| 文件大小： | 690K |
| 代理商： | LM5067SDX-1 |
(R
S), connected from SENSE to VEE. The required resistor
value is calculated from:
(1)
where I
LIM is the desired current limit threshold. When the
voltage across R
S reaches 50 mV, the current limit circuit
modulates the gate of Q1 to regulate the current at I
LIM. While
the current limiting circuit is active, the fault timer is active as
described in the Fault Timer & Restart section. For proper
operation, R
S must be no larger than 100 m.
While the maximum load current in normal operation can be
used to determine the required power rating for resistor R
S,
basing it on the current limit value provides a more reliable
design since the circuit can operate near the current limit
threshold continuously. The resistor’s surge capability must
also be considered since the circuit breaker threshold is ap-
proximately twice the current limit threshold. Connections
from R
S to the LM5067 should be made using Kelvin tech-
niques. In the suggested layout of Figure 7 the small pads at
the upper corners of the sense resistor connect only to the
sense resistor terminals, and not to the traces carrying the
high current. With this technique, only the voltage across the
sense resistor is applied to VEE and SENSE, eliminating the
voltage drop across the high current solder connections.
30030935
FIGURE 7. Sense Resistor Connections
POWER LIMIT THRESHOLD
The LM5067 determines the power dissipation in the external
MOSFET (Q1) by monitoring the drain current (the current in
R
S), and the VDS of Q1 (OUT to SENSE pins). The resistor at
the PWR pin (R
PWR) sets the maximum power dissipation for
Q1, and is calculated from the following equation:
R
PWR = 1.42 x 10
5
x R
S x PFET(LIM)
(2)
where P
FET(LIM) is the desired power limit threshold for Q1,
and R
S is the current sense resistor described in the Current
Limit section. For example, if R
S is 10 m, and the desired
power limit threshold is 60W, R
PWR calculates to 85.2 k. If
Q1’s power dissipation reaches the power limit threshold,
Q1’s gate is modulated to control the load current, keeping
Q1’s power from exceeding the threshold. For proper opera-
tion of the power limiting feature, R
PWR must be ≤150 k.
While the power limiting circuit is active, the fault timer is ac-
tive as described in the Fault Timer & Restart section. Typi-
cally, power limit is reached during startup, or when the V
DS
of Q1 increases due to a severe overload or short circuit.
The programmed maximum power dissipation should have a
reasonable margin relative to the maximum power defined by
the SOA chart if the LM5067-2 is used since the FET will be
repeatedly stressed during fault restart cycles. The FET man-
ufacturer should be consulted for guidelines. The PWR pin
can be left open if the application does not require use of the
power limit function.
TURN-ON TIME
The output turn-on time depends on whether the LM5067 op-
erates in current limit only, or in both power limit and current
limit, during turn-on.
A) Turn-on with current limit only:
If the current limit thresh-
old is less than the current defined by the power limit threshold
at maximum V
DS the circuit operates only at the current limit
threshold during turn-on. Referring to Figure 10a, as the drain
current reaches I
LIM, the gate-to-source voltage is controlled
at V
GSL to maintain the current at ILIM. As the output voltage
reaches its final value (V
DS 0V) the drain current reduces
to the value defined by the load, and the gate is charged to
approximately 13V (V
GATE). The time for the OUT pin voltage
to transition from zero volts to V
SYS is equal to:
where C
L is the load capacitance. For example, if VSYS = -48V,
C
L = 1000 F, and ILIM = 1A, tON calculates to 48 ms. The
maximum instantaneous power dissipated in the MOSFET is
48W. This calculation assumes the time from t1 to t2 in Figure
10a is small compared to t
ON, and the load does not draw any
current until after the output voltage has reached its final val-
ue, and PGD switches high (Figure 8).
30030937
FIGURE 8. No Load Current During Turn-on
If the load draws current during the turn-on sequence (Figure
9), the turn-on time is longer than the above calculation, and
is approximately equal to:
where R
L is the load resistance and VSYS is the absolute value
of the system input voltage. The Fault Timeout Period must
be set longer than t
ON to prevent a fault shutdown before
the turn-on sequence is complete.
www.national.com
14
LM5067
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