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参数资料
| 型号： | LM5067SDX-1 |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 电源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, DSO10 |
| 封装： | LLP-10 |
| 文件页数： | 8/24页 |
| 文件大小： | 690K |
| 代理商： | LM5067SDX-1 |
MOSFET SELECTION
It is recommended that the external MOSFET (Q1) selection
be based on the following criteria:
-
The BV
DSS rating should be greater than the maximum
system voltage (V
SYS), plus ringing and transients which can
occur at V
SYS when the circuit card, or adjacent cards, are
inserted or removed.
-
The maximum continuous current rating should be based
on the current limit threshold (50 mV/R
S), not the maximum
load current, since the circuit can operate near the current
limit threshold continuously.
-
The Pulsed Drain Current spec (I
DM) must be greater than
the current threshold for the circuit breaker function (100 mV/
R
S).
-
The SOA (Safe Operating Area) chart of the device, and
the thermal properties, should be used to determine the max-
imum power dissipation threshold set by the R
PWR resistor.
The programmed maximum power dissipation should have a
reasonable margin from the maximum power defined by the
FET's SOA chart if the LM5067-2 is used since the FET will
be repeatedly stressed during fault restart cycles. The FET
manufacturer should be consulted for guidelines.
-
R
DS(on) should be sufficiently low that the power dissipa-
tion at maximum load current (I
L(max)
2
x R
DS(on)) does not raise
its junction temperature above the manufacturer’s recom-
mendation.
If the device chosen for Q1 has a maximum V
GS rating less
than 13V, an external zener diode must be added from its gate
to source, with the zener voltage less than the maximum
V
GS rating. The zener diode’s forward current rating must be
at least 110 mA to conduct the GATE pull-down current during
startup and in the circuit breaker mode.
TIMER CAPACITOR, C
T
The TIMER pin capacitor (C
T) sets the timing for the insertion
time delay, fault timeout period, and restart timing of the
LM5067-2.
A) Insertion Delay
- Upon applying the system voltage
(V
SYS) to the circuit, the external MOSFET (Q1) is held off
during the insertion time (t1 in Figure 3) to allow ringing and
transients at V
SYS to settle. Since each backplane’s response
to a circuit card plug-in is unique, the worst case settling time
must be determined for each application. The insertion time
starts when the operating voltage (VCC-VEE) reaches the
POR
IT threshold, at which time the internal 6 A current
source charges C
T from 0V to 4.0V. The required capacitor
value is calculated from:
where t1 is the desired insertion delay. For example, if the
desired insertion delay is 250 ms, C
T calculates to 0.38 F.
At the end of the insertion delay, C
T is quickly discharged by
a 1.5 mA current sink.
B) Fault Timeout Period
- During turn-on of the output volt-
age, or upon detection of a fault condition where the current
limit and/or power limit circuits regulate the current through
Q1, C
T is charged by the fault timer current source (85 A).
The Fault Timeout Period is the time required for the TIMER
pin voltage to reach 4.0V above VEE, at which time Q1 is
switched off. The required capacitor value for the desired
Fault Timeout Period t
FAULT is calculated from:
(3)
For example, if the desired Fault Timeout Period is 16 ms,
C
T calculates to 0.34 F. After a fault timeout, if the LM5067-1
is in use, C
T must be allowed to discharge to <0.3V by the 2.5
A current sink, after which a power up sequence can be ini-
tiated by external circuitry. See the Fault Timer and Restart
section and Figure 5. If the LM5067-2 is in use, after the Fault
Timeout Period expires a restart sequence begins as de-
scribed below (Restart Timing).
Since the LM5067 normally operates in power limit and/or
current limit during a power up sequence, the Fault Timeout
Period MUST be longer than the time required for the output
voltage to reach its final value. See the Turn-on Time section.
C) Restart Timing
If the LM5067-2 is in use, after the Fault
Timeout Period described above, C
T is discharged by the 2.5
A current sink to 1.25V. The TIMER pin then cycles through
seven additional charge/discharge cycles between 1.25V and
4.0V as shown in Figure 6. The restart time ends when the
TIMER pin voltage reaches 0.3V during the final high-to-low
ramp. The restart time, after the Fault Timeout Period, is equal
to:
= C
T x 9.4 x 10
6
For example, if C
T = 0.33 F, tRESTART = 3.1 seconds. At the
end of the restart time, Q1 is switched on. If the fault is still
present, the fault timeout and restart sequence repeats. The
on-time duty cycle of Q1 is approximately 0.5% in this mode.
UVLO, OVLO
By programming the UVLO and OVLO thresholds the
LM5067 enables the series pass device (Q1) when the input
supply voltage (V
SYS) is within the desired operational range.
If V
SYS is below the UVLO threshold, or above the OVLO
threshold, Q1 is switched off, denying power to the load. Hys-
teresis is provided for each threshold.
Note: All voltages are with respect to Vee in the discus-
sions below. Use absolute values in the equations.
Option A:
The configuration shown in Figure 11 requires
three resistors (R1-R3) to set the thresholds.
30030946
FIGURE 11. UVLO and OVLO Thresholds Set By R1-R3
www.national.com
16
LM5067
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