AC Electrical Characteristics
The following specifications apply for +3.0 V
DC ≤ V
+
≤ +5.5 V
DC , unless otherwise specified. Boldface limits apply for TA = TJ
= T
MIN to TMAX; all other limits T
Symbol
Parameter
Conditions
Typical
Limits
Units
(Limits)
SERIAL BUS TIMING CHARACTERISTICS
t
1
SCL (Clock) Period
2.5
100
μs (min)
μs (max)
t
2
Data In Setup Time to SCL High
100
ns (min)
t
3
Data Out Stable After SCL Low
0
ns (min)
t
4
SDA Low Setup Time to SCL Low (start)
100
ns (min)
t
5
SDA High Hold Time After SCL High (stop)
100
ns (min)
t
TIMEOUT
SCL or SDA time low for I2C bus reset
25
35
ms (min)
ms (max)
30070126
FIGURE 1. Serial Bus Timing Diagram
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2:
All voltages are measured with respect to GND, unless otherwise specified
Note 3:
When the input voltage (V
IN) at any pin exceeds the power supplies (VIN< (GND or GNDA) or VIN>V
+
), the current at that pin should be limited to 5 mA.
The 30 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to six pins.
Parasitic components and/or ESD protection circuitry are shown in the Pin Descriptions table.
Note 4:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
Jmax, θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is P
D = (TJmaxT A)/θJA.
Note 5:
Human body model (HBM) is a charged 100 pF capacitor discharged into a 1.5 k
Ω resistor. Machine model (MM), is a charged 200 pF capacitor discharged
directly into each pin. Charged Device Model (CDM) simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated
assembler) then rapidly being discharged.
Note 6:
Reflow temperature profiles are different for packages containing lead (Pb) than for those that do not..
Note 7:
Each input and output is protected by an ESD structure to GND, as shown in the Pin Descriptions table. Input voltage magnitude up to 0.3V above V+ or
0.3V below GND will not damage the LM96080. There are parasitic diodes that exist between some inputs and the power supply rails. Errors in the ADC conversion
can occur if these diodes are forward biased by more than 50 mV. As an example, if V+ is 4.50 V
DC, input voltage must be ≤ 4.55 VDC, to ensure accurate
conversions.
Note 8:
Typicals are at T
J= TA= 25°C and represent most likely parametric norm.
Note 9:
Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 10:
TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC.
Note 11:
Limit is guaranteed by Design.
Note 12:
Total Monitoring Cycle Time includes temperature conversion, 7 analog input voltage conversions and 2 tachometer readings. For more information
on the conversion rates, refer to the description of bit 0, register 07h in section 13.0: Registers and RAM.
Note 13:
The total fan count is based on 2 pulses per revolution of the fan tachometer output.
Note 14:
Timing specifications are tested at the Serial Bus Input logic levels, V
IN(0) = 0.3 × V
+
for a falling edge and V
IN(1) = 0.7 × V
+
for a rising edge when the
SCL and SDA edge rates are similar.
7
www.national.com
LM96080