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参数资料
| 型号： | LM9823CCWM/NOPB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封装： | 0.300 INCH, PLASTIC, SOIC-28 |
| 文件页数： | 11/22页 |
| 文件大小： | 238K |
| 代理商： | LM9823CCWM/NOPB |
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the OS input, the maximum allowable droop, the number of pixels
on the sensor, and the pixel conversion rate, fVSMP, and provides
the minimum clamp capacitor value:
For example, if the OS input leakage current is 25nA worst-case,
the sensor has 2700 active pixels, the conversion rate is 2MHz
(tVSMP = 500ns), and the max droop desired is 0.1V, the minimum
clamp capacitor value is:
6.1.2 CIS mode Minimum Clamp Capacitor Calculation:
If CDS is disabled, then the maximum LM9823 OS input leakage
current can be calculated from:
where VSAT is the peak pixel signal swing of the CIS OS output
and CSAMP is the capacitance of the LM9823 internal sampling
capacitor (2pF). Inserting this into Equation 6 results in:
with CSAMP equal to 2pF and VSAT equal to 2V (the LM9823 max-
imum input signal), then Equation 9 reduces to:
In CIS mode (CDS disabled), the max droop limit must be much
more carefully chosen, since any change in the clamp capacitor’s
DC value will affect the LM9823 conversion results. If a droop of
one 10 bit LSB across a line is considered acceptable, then the
allowed droop voltage is calculated as: 2V/1024, or approximately
2mV. If there are 2700 active pixels on a line then:
6.1.3 Maximum Clamp Capacitor Calculation:
The maximum size of the clamp capacitor is determined by the
amount of time available to charge it to the desired value during
the optical black portion of the sensor output. The internal clamp
occurs when CLMP and VSMP are both high on a rising edge of
MCLK. If SMPCL=0, the clamps are on immediately before the
sample reference time, if SMPCL=1, the clamps are on immedi-
ately after the sample reference time. If the LM9823 is operated
in divide by 2 mode, then the clamp is on 50% of the time when
CLMP is high. In this case the available charge time per line can
be calculated using:
For example, if a sensor has 18 black reference pixels and fVSMP
is 2MHz with a 50% duty cycle, then tCLAMP is 4.5s. Other
“divide by” modes will have lower or higher clamp duty cycles
accordingly, depending on the SMPCL setting. See Diagram 8,
Clamp Timing With SMPCL = 0 and Diagram 9, Clamp Timing
With SMPCL = 1.
The following equation takes the number of optical black pixels,
the amount of time (per pixel) that the clamp is closed, the sen-
sor’s output impedance, and the desired accuracy of the final
clamp voltage and provides the maximum clamp capacitor value
that allows the clamp capacitor to settle to the desired accuracy
within a single line:
Where tCLAMP is the amount of time (per line) that the clamp is
on, RCLAMP is the output impedance of the CCD plus 50 for the
LM9823 internal clamp switch, and accuracy is the ratio of the
worst-case initial capacitor voltage to the desired final capacitor
voltage. If tCLAMP is 4.5s, the output impedance of the sensor is
1500
, the worst case voltage change required across the capac-
itor (before the first line) is 5V, and the desired accuracy after
clamping is to within 0.1V (accuracy = 5/0.1 = 50), then:
The final value for CCLAMP should be less than or equal to
CCLAMP MAX, but no less than CCLAMP MIN.
In some cases, depending primarily on the choice of sensor,
CCLAMP MAX may actually be less than CCLAMP MIN, meaning that
the capacitor can not be charged to its final voltage during the
black pixels at the beginning of a line and hold it’s voltage without
drooping for the duration of that line. This is usually not a problem
because in most applications the sensor is clocked continuously
as soon as power is applied. In this case, a larger capacitor can
be used (guaranteeing that the CCLAMP MIN requirement is met),
and the final clamp voltage is forced across the capacitor over
multiple lines. This equation calculates how many lines are
required before the capacitor settles to the desired accuracy:
Using the values shown before and a clamp capacitor value of
0.01F, this works out to be:
In this example, a 0.01F capacitor takes 14 lines after power-up
to charge to its final value. On subsequent lines, the only error will
be the droop across a single line which should be significantly
C
CLAMP MIN
i
dV
---------dt
=
leakage current (A)
max droop(V)
---------------------------------------------------
number of pixels
f
VS MP
--------------------------------------------
=
Equation 6. CDS mode CCLAMP MIN Calculation
C
CLAMP MIN
25nA
0.1V
--------------
2700
2MHz
---------------
=
340pF
=
Equation 7. CDS mode CCLAMP MIN Example
I
leakage
V
SAT fSampCLK CSA MP
=
Equation 8. CIS mode Input Leakage Current Calculation
C
CLAMP MIN
i
dV
---------dt
=
V
SAT
t
SampCLK
---------------------------C
SAMP
t
SampCLK
max droop(V)
------------------------------------ num pixels
=
Equation 9. CIS mode CCLAMP MIN Calculation
C
CLAMP MIN
4p(F)(V)
max droop(V)
------------------------------------num pixels
=
Equation 10. CIS mode CCLAMP MIN Calculation
C
CLAMP MIN
4p(F)(V)
2mV
----------------------2700
=
Equation 11. CIS mode CCLAMP MIN Calculation Example
5.4uF
=
t
CLAMP
Number of optical black pixels
2f
VSMP
-------------------------------------------------------------------------------
=
Equation 12. Clamp Time Per Line Calculation
C
CLAMP MAX
t
R
------
1
ln(accuracy)
--------------------------------
=
t
CLAMP
R
CLAMP
--------------------------
1
ln(accuracy)
--------------------------------
=
Equation 13. CCLAMP MAX for a single line of charge time
C
CLAMP MAX
4.5
s
1550
------------------
1
ln(50)
---------------
=
728 pF
=
Equation 14. CCLAMP MAX Example
lines
R
CLAMP
C
CLAMP
t
CLAMP
-------------------------
Initial Error Voltage
Final Error Voltage
----------------------------------------------------
ln
=
Equation 15. Number of Lines Required for Clamping
lines
1550
0.01
F
4.5
s
-------------------
5V
0.1V
------------
ln
13.5 lines
==
Equation 16. Clamping Lines Required Example
L
M
9
823
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