- 您现在的位置：买卖IC网 > PDF目录67756 > LM9823CCWM/NOPB (NATIONAL SEMICONDUCTOR CORP) SPECIALTY ANALOG CIRCUIT, PDSO28 PDF资料下载
参数资料
| 型号： | LM9823CCWM/NOPB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封装： | 0.300 INCH, PLASTIC, SOIC-28 |
| 文件页数： | 9/22页 |
| 文件大小： | 238K |
| 代理商： | LM9823CCWM/NOPB |
17
www.national.com
Applications Information
1.0 Introduction
The LM9823 is a high performance scanner Analog Font End
(AFE) for image sensor processing systems. It is designed to
work with color CCD and CIS image sensors and provides a full 3
channel sampling, gain and offset correction system, coupled
with a 16 bit high speed analog to digital converter. A typical
application of the LM9823 is in a color flatbed document scanner.
The image sensing and processing portion of the system would
be configured similar to that shown in Figure 1.
Figure 1. LM9823 in Basic Color Scanner
2.0 CDS Correlated Double Sampler
The LM9823 uses a high-performance CDS (Correlated Double
Sampling) circuit to remove many sources of noise and error from
the image sensor output signal. It also supports CIS image sen-
sors with a single ended sampling mode.
Figure 2 shows the output stage of a typical CCD and the result-
ing output waveform:
Figure 2. CDS
Capacitor C1 converts the electrons coming from the CCD’s shift
register to an analog voltage. The source follower output stage
(Q2) buffers this voltage before it leaves the CCD. Q1 resets the
voltage across capacitor C1 between pixels at intervals 2 and 5.
When Q1 is on, the output signal (OS) is at its most positive volt-
age. After Q1 turns off (period 3), the OS level represents the
residual voltage across C1 (VRESIDUAL). VRESIDUAL includes
charge injection from Q1, thermal noise from the ON resistance
of Q1, and other sources of error. When the shift register clock
(1) makes a low to high transition (period 4), the electrons from
the next pixel flow into C1. The charge across C1 now contains
the voltage proportional to the number of electrons plus VRESID-
UAL, an error term. If OS is sampled at the end of period 3 and
that voltage is subtracted from the OS at the end of period 4, the
VRESIDUAL term is canceled and the noise on the signal is
reduced ([VSIGNAL+VRESIDUAL]-VRESIDUAL = VSIGNAL). This is the
principal of Correlated Double Sampling.
3.0 CIS Mode (CDS Off, Selectable Signal Polarity)
The also LM9823 supports CIS (Contact Image Sensor) devices.
The output signal of a CIS sensor (Figure 3) differs from a CCD
signal in two primary ways: its output usually increases with
increasing signal strength, and it does not usually have a refer-
ence level as an integral part of the output waveform of every
pixel.
Figure 3. CIS
When the LM9823 is in CIS (CDS off) mode (Register 0, B5=1), it
uses either VREF+ or VREF- as the reference (or black) voltage for
each pixel (depending on the signal polarity setting (Register 0,
Bit 4)). If the signal polarity is set to one, then VREF- will be sam-
pled as the reference level. If it is set to zero, then VREF+ will be
sampled as the reference level.
4.0 Programmable Gain
The output of the Sampler drives the input of the x3 Boost gain
stage. The gain of each x3 Boost gain is 3V/V if bit B5 of that
color’s gain register (register 4,5, or 6) is set, or 1V/V if bit B5 is
cleared. The output of each x3 gain stage is the input an offset
DAC and the output of each offset DAC is the input to a PGA
(Programmable Gain Amplifier). Each PGA provides 5 bits of gain
correction over a 0.93V/V to 3V/V (-0.6 to 9.5dB) range. The x3
Boost gain stage and the PGA can be combined for an overall
gain range of 0.93V/V to 9.0V/V (-.6 to 19dB). The gain setting for
each color (registers 4, 5 and 6) should be set during calibration
to bring the maximum amplitude of the strongest pixel to a level
just below the desired maximum output from the ADC. The PGA
gain is determined by the following equation:
If the x3 Boost gain is enabled then the overall signal gain will be
three times the PGA gain.
ASIC
LM982
3
CC
D
RAM
8 Output Data
8
OSR
OSG
OSB
CCD Control
AFE Control
To Host
Other scanner elements
omitted for simplicity.
RS (RESET)
e-
(from shift register)
OS
Q1
Q2
C1
VDD
VSS
1
RS
OS
12
3
4
5
OS (CCD)
12
3
4
5
OS (CIS)
PGA Gain
V
----
0.933 + .0667 (value in bits B4-B0)
=
Equation 1. PGA Gain
L
M
9
823
相关PDF资料 |
PDF描述 |
|---|---|
| LM9823CCWMX/NOPB | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| LMX1602MDA | PLL FREQUENCY SYNTHESIZER, 1100 MHz, UUC |
| LMX2305WG-MLSX | PLL FREQUENCY SYNTHESIZER, 500 MHz, CDSO20 |
| LMX2305WG-MPR | PLL FREQUENCY SYNTHESIZER, 550 MHz, CDSO20 |
| 5962-9855003QXA | PLL FREQUENCY SYNTHESIZER, 550 MHz, CDSO20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LM9823CCWMX | 制造商:NSC 制造商全称:National Semiconductor 功能描述:LM9823 3 Channel 48-Bit Color Scanner Analog Front End |
| LM9830 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:LM9830 36-Bit Color Document Scanner |
| LM9830VJD | 功能描述:视频模拟/数字化转换器集成电路 RoHS:否 制造商:Texas Instruments 输入信号类型:Differential 转换器数量:1 ADC 输入端数量:4 转换速率:3 Gbps 分辨率:8 bit 结构: 输入电压:3.3 V 接口类型:SPI 信噪比: 电压参考: 电源电压-最大:3.45 V 电源电压-最小:3.15 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:TCSP-48 封装:Reel |
| LM9830VJD/NOPB | 功能描述:视频模拟/数字化转换器集成电路 RoHS:否 制造商:Texas Instruments 输入信号类型:Differential 转换器数量:1 ADC 输入端数量:4 转换速率:3 Gbps 分辨率:8 bit 结构: 输入电压:3.3 V 接口类型:SPI 信噪比: 电压参考: 电源电压-最大:3.45 V 电源电压-最小:3.15 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:TCSP-48 封装:Reel |
| LM9830VJDX | 制造商:NSC 制造商全称:National Semiconductor 功能描述:LM9830 36-Bit Color Document Scanner |
发布紧急采购，3分钟左右您将得到回复。