Symbol
Parameter
Conditions
Min
Typ
Max
Units
Clock Distribution Section
(Note 7) - LVPECL Clock Outputs (CLKout3 to CLKout7) Jitter
ADD
Additive RMS Jitter (Note
7)R
L = 100 Ω
Input Bus = 800
MHz
Integration
Bandwidth = 12 kHz
to 20 MHz
CLKoutX_MUX
= Bypass
40
fs
CLKoutX_MUX
= Divided
CLKoutX_DIV =
4
150
t
SKEW
CLKoutX to CLKoutY
Equal loading and identical channel
configuration
Termination = 50
Ω to Vcc - 2 V
-30
±3
30
ps
V
OH
Output High Voltage
Termination = 50
Ω to Vcc - 2 V
Vcc -
0.98
V
OL
Output Low Voltage
Vcc -
1.8
V
OD
Differential Output Voltage
660
810
965
mV
Digital LVTTL Interfaces
V
IH
High-Level Input Voltage
2.0
Vcc
V
IL
Low-Level Input Voltage
0.8
V
I
IH
High-Level Input Current
V
IH = Vcc
-1.0
1.0
A
I
IL
Low-Level Input Current
V
IL = 0
-1.0
1.0
A
V
OH
High-Level Output Voltage
I
OH = -500 A
Vcc -
0.4
V
OL
Low-Level Output Voltage
I
OL = -500 A
0.4
V
Digital MICROWIRE Interfaces
V
IH
High-Level Input Voltage
1.6
Vcc
V
IL
Low-Level Input Voltage
0.4
V
I
IH
High-Level Input Current
V
IH = Vcc
-1.0
1.0
A
I
IL
Low-Level Input Current
V
IL = 0
-1.0
1.0
A
MICROWIRE Timing
t
CS
Data to Clock Set Up Time
See Data Input Timing
25
ns
t
CH
Data to Clock Hold Time
See Data Input Timing
8
ns
t
CWH
Clock Pulse Width High
See Data Input Timing
25
ns
t
CWL
Clock Pulse Width Low
See Data Input Timing
25
ns
t
ES
Clock to Enable Set Up Time
See Data Input Timing
25
ns
t
CES
Enable to Clock Set Up Time
See Data Input Timing
25
ns
t
EWH
Enable Pulse Width High
See Data Input Timing
25
ns
Note 3:
For all frequencies the slew rate, SLEW
OSCin, is measured between 20% and 80%. If only OSCin is being driven (OSCin* AC grounded), the slew rate
is half, 0.25 V/ns.
Note 4:
For all frequencies the slew rate, SLEW
Fin, is measured between 20% and 80%. If only Fin is being driven (Fin* AC grounded), the slew rate is half, 0.25
V/ns.
Note 5:
A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L
PLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10
dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = L
PLL_flicker(10 kHz) - 20log(Fout / 1 GHz), where LPLL_flicker
(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure L
PLL_flicker(f) it is important to be on the 10 dB/decade
slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f).
Note 6:
A specification in modeling PLL in-band phase noise is the Normalized Phase Noise Contribution, L
PLL_flat(f), of the PLL and is defined as: PN1Hz =
L
PLL_flat(f) – 20log(N) – 10log(Fcomp). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz Bandwidth and Fcomp is the
comparison frequency of the synthesizer. L
PLL_flat(f) contributes to the total noise, L(f). To measure LPLL_flat(f) the offset frequency, f, must be chosen sufficiently
smaller then the loop bandwidth of the PLL, and yet large enough to avoid a substantial noise contribution from the reference and flicker noise.
Note 7:
The Clock Distribution Section includes all parts of the device except the PLL section. Typical Additive Jitter specifications apply to the clock distribution
section only.
Note 8:
Applies to GOE, LD, and SYNC*.
Note 9:
Applies to uWireCLK, uWireDATA, and uWireLE.
5
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