参数资料
型号: LMK02000
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 时钟及定时
英文描述: Precision Clock Conditioner with Integrated PLL
中文描述: 2000 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC48
封装: 7 X 7 MM, 0.80 MM HEIGHT, LLP-48
文件页数: 4/18页
文件大小: 377K
代理商: LMK02000
2.2 REGISTER R0 to R7
Registers R0 through R7 control the eight clock output pins. Register R0 controls CLKout0, Register R1 controls CLKout1, and so
on. Aside from this, the functions of these bits are identical. The X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and
CLKoutX_EN denote the actual clock output which may be from 0 to 7.
2.2.1 CLKoutX_MUX[1:0] -- Clock Output Multiplexers
These bits control the Clock Output Multiplexer for each pin. Changing between the different modes changes the blocks in the
signal path and therefore incurs a delay relative to the bypass mode. The different MUX modes and associated delays are listed
below.
CLKoutX_MUX[1:0]
Mode
Added Delay Relative to Bypass Mode
0
Bypassed
0 ps
1
Divided
100 ps
2
Delayed
400 ps
(In addition to the programmed delay)
3
Divided and Delayed
500 ps
(In addition to the programmed delay)
2.2.2 CLKoutX_DIV[7:0] -- Clock Output Dividers
These bits control the clock output divider value. In order for these dividers to be active, the respective CLKoutX_MUX (See 2.2.1)
bit must be set to either "Divided" or "Divided and Delayed" mode. After all the dividers are programed, the SYNC* pin must be
used to ensure that all edges of the clock output pins are aligned (See 1.7). The Clock Output Dividers follow the Input Divider so
the final clock divide for an output is Input Divider x Clock Output Divider. By adding the divider block to the output path a fixed
delay of approximately 100 ps is incurred.
The actual Clock Output Divide value is twice the binary value programmed as listed in the table below.
CLKoutX_DIV[7:0]
Clock Output Divider value
0
Invalid
0
1
2
0
1
0
4
0
1
6
0
1
0
8
0
1
0
1
10
.
...
1
510
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LMK02000
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