1.0 Functional Description
The LMK02000 precision clock conditioner combines the
functions of jitter cleaning/reconditioning, multiplication, and
distribution of a reference clock. The device integrates a high
performance Integer-N Phase Locked Loop (PLL), three
LVDS, and five LVPECL clock output distribution blocks.
Each clock distribution block includes a programmable di-
vider, a phase synchronization circuit, a programmable delay,
a clock output mux, and an LVDS or LVPECL output buffer.
This allows multiple integer-related and phase-adjusted
copies of the reference to be distributed to eight system com-
ponents.
The clock conditioner comes in a 48-pin LLP package and is
footprint compatible with other clocking devices in the same
family.
1.1 BIAS PIN
To properly use the device, bypass Bias (pin 36) with a low
leakage 1 F capacitor connected to Vcc. This is important
for low noise performance.
1.2 LDO BYPASS
To properly use the device, bypass LDObyp1 (pin 9) with a
10 F capacitor and LDObyp2 (pin 10) with a 0.1 F capacitor.
1.3 OSCILLATOR INPUT PORT (OSCin, OSCin*)
The purpose of OSCin is to provide the PLL with a reference
signal. The OSCin port may be driven single endedly by AC
grounding OSCin*.
1.4 FREQUENCY INPUT PORT (Fin, Fin*)
The purpose of Fin is to provide the PLL with a feedback sig-
nal from an external oscillator. The Fin port may be driven
single endedly by AC grounding Fin*.
1.5 CLKout DELAYS
Each individual clock output includes a delay adjustment.
Clock output delay registers (CLKoutX_DLY) support a 150
ps step size and range from 0 to 2250 ps of total delay.
1.6 LVDS/LVPECL OUTPUTS
Each LVDS or LVPECL output may be disabled individually
by programming the CLKoutX_EN bits. All the outputs may
be disabled simultaneously by pulling the GOE pin low or
programming EN_CLKout_Global to 0.
1.7 GLOBAL CLOCK OUTPUT SYNCHRONIZATION
The SYNC* synchronizes the clock outputs. When SYNC* is
held in a logic low state, the outputs are also held in a logic
low state. When SYNC* goes high, the clock outputs are ac-
tivated and will transition to a high state simultaneously.
SYNC* must be held low for greater than one clock cycle of
the Input Channel Bus. Once this low event has been regis-
tered, the outputs will not reflect the low state for four more
cycles. Similarly once SYNC* becomes high, the outputs will
not simultaneously transition high until four more Input Chan-
nel Bus clock cycles have passed. See the timing diagram
below for further detail.
SYNC* Timing Diagram
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1.8 GLOBAL OUTPUT ENABLE AND LOCK DETECT
Each clock output may be individually enabled. Each output
enable control bit is gated with the Global Output Enable input
pin
(GOE)
and
the
Global
Output
Enable
bit
(EN_CLKout_Global).
The GOE pin provides an internal pull-up. If it is unterminated
externally, the clock output states are determined by the
Clock Output Enable bits (CLKoutX_EN).
All clock outputs can be disabled simultaneously if the GOE
pin is pulled low by an external signal or EN_CLKout_Global
is set to 0.
The Lock Detect (LD) signal can be connected to the GOE
pin in which case all outputs are disabled automatically if the
synthesizer is not locked.
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LMK02000