参数资料
型号: LMK02000
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 时钟及定时
英文描述: Precision Clock Conditioner with Integrated PLL
中文描述: 2000 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC48
封装: 7 X 7 MM, 0.80 MM HEIGHT, LLP-48
文件页数: 7/18页
文件大小: 377K
代理商: LMK02000
2.4 Register R15
2.4.1 PLL_N[17:0] -- PLL N Divider
These bits program the divide value for the PLL N Divider. The PLL N Divider follows the Input Divider and precedes the PLL phase
detector. Since the Input Divider is also in the feedback path from the VCO to the PLL Phase Detector, the total N divide value,
N
Total, is also influenced by the Input Divider value. NTotal = PLL N Divider * Input Divider. The VCO frequency is calculated as,
f
VCO = fOSCin * PLL N Divider * Input Divider / R. Since the PLL N divider is a pure binary counter, there are no illegal divide values
for PLL_N[17:0].
PLL_N[17:0]
PLL N Divider Value
0
Invalid
0
1
.
...
1
262143
2.4.2 INPUT_DIV[3:0] -- Input Divider
These bits program the divide value for the Input Divider. The Input Divider follows the VCO output and precedes the clock distri-
bution blocks. Since the Input Divider is in the feedback path from the VCO to the PLL phase detector the Input Divider contributes
to the total N divide value, N
Total. NTotal = PLL N Divider * Input Divider. The Input Divider can not be bypassed. See 2.4.1 (PLL N
Divider) for more information on setting the VCO frequency.
INPUT_DIV[3:0]
Input Divider Value
0
Invalid
0
1
Invalid
0
1
0
2
0
1
3
0
1
0
4
0
1
0
1
5
0
1
0
6
0
1
7
1
0
8
1
0
1
Invalid
.
...
1
Invalid
2.4.3 PLL_CP_GAIN[1:0] -- PLL Charge Pump Gain
These bits set the charge pump gain of the PLL.
PLL_CP_GAIN[1:0]
Charge Pump Gain
0
1x
1
4x
2
16x
3
32x
15
www.national.com
LMK02000
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