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参数资料
| 型号： | LMR10510YSDX/NOPB |
| 厂商： | National Semiconductor |
| 文件页数： | 12/26页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 1A 6LLP |
| 标准包装： | 4,500 |
| 系列： | SIMPLE SWITCHER® |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 4.5 V |
| 输入电压： | 3 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 3MHz |
| 电流 - 输出： | 1A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-WDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 6-LLP-EP（3x3） |
SNVS727B – OCTOBER 2011 – REVISED APRIL 2013
I D1 = I OUT x (1-D)
The reverse breakdown rating of the diode must be at least the maximum input voltage plus appropriate margin.
To improve efficiency, choose a Schottky diode with a low forward voltage drop.
OUTPUT VOLTAGE
The output voltage is set using the following equation where R2 is connected between the FB pin and GND, and
R1 is connected between V O and the FB pin. A good value for R2 is 10k ? . When designing a unity gain
converter (Vo = 0.6V), R1 should be between 0 ? and 100 ? , and R2 should be equal or greater than 10k ? .
R1 =
V OUT
V REF
- 1 x R2
V REF = 0.60V
PCB LAYOUT CONSIDERATIONS
When planning layout there are a few things to consider when trying to achieve a clean, regulated output. The
most important consideration is the close coupling of the GND connections of the input capacitor and the catch
diode D1. These ground ends should be close to one another and be connected to the GND plane with at least
two through-holes. Place these components as close to the IC as possible. Next in importance is the location of
the GND connection of the output capacitor, which should be near the GND connections of CIN and D1. There
should be a continuous ground plane on the bottom layer of a two-layer board except under the switching node
island. The FB pin is a high impedance node and care should be taken to make the FB trace short to avoid noise
pickup and inaccurate regulation. The feedback resistors should be placed as close as possible to the IC, with
the GND of R1 placed as close as possible to the GND of the IC. The V OUT trace to R2 should be routed away
from the inductor and any other traces that are switching. High AC currents flow through the V IN , SW and V OUT
traces, so they should be as short and wide as possible. However, making the traces wide increases radiated
noise, so the designer must make this trade-off. Radiated noise can be decreased by choosing a shielded
inductor. The remaining components should also be placed as close as possible to the IC. Please see
Application Note AN-1229 for further considerations and the LMR10510 demo board as an example of a good
layout.
Calculating Efficiency, and Junction Temperature
The complete LMR10510 DC/DC converter efficiency can be calculated in the following manner.
Or
K =
K =
P OUT
P IN
P OUT
P OUT + P LOSS
Calculations for determining the most significant power losses are shown below. Other losses totaling less than
2% are not discussed.
Power loss (P LOSS ) is the sum of two basic types of losses in the converter: switching and conduction.
Conduction losses usually dominate at higher output loads, whereas switching losses remain relatively fixed and
dominate at lower output loads. The first step in determining the losses is to calculate the duty cycle (D):
D=
V OUT + V D
V IN + V D - V SW
V SW is the voltage drop across the internal PFET when it is on, and is equal to:
V SW = I OUT x R DSON
V D is the forward voltage drop across the Schottky catch diode. It can be obtained from the diode manufactures
Electrical Characteristics section. If the voltage drop across the inductor (V DCR ) is accounted for, the equation
becomes:
12
Product Folder Links: LMR10510
Copyright ? 2011–2013, Texas Instruments Incorporated
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| LMR10515XMFE | 制造商:TI 制造商全称:Texas Instruments 功能描述:SIMPLE SWITCHER? 5.5Vin, 1.5A Step-Down Voltage Regulator in SOT-23 and LLP |
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